DRV8328: standalone testing of the DRV8328

Hi Giorgio,

Giorgio Valente said:

I'm assembling the PCB for a 1kW inverter that I've designed for a BLDC motor application. I got to the stage where I've just hand soldered the gate driver DRV8328ARUYR and I would like to test it on its own to make sure I've properly soldered all the pins to the pads and I've not damaged the device (I used a heat gun to do the soldering) before soldering the MOSFETs devices on the power stage and the MCU. The components I soldered are represented in the schematic below:

This schematic and component values look correct. Make sure each capacitor is rated for 2x the voltage they are biased at. 

Giorgio Valente said:

where PVDD is the main supply (36V); SPEEP, INHA, INLA, INHB, INLB, INHC, INLC and FAULT are routed directly the TMS320F28034PNS uC; DT and VDSLVL are connected to 2 POTs (see snapshots below); GHA, GLA, GHB, GLB, GHC, GLC are routed to the MOSFETs gates through the external gate resistance; SHA, SHB, SHC are routed to the sources of the high side MOSFETs and LSS is routed to the sources of the low side MOSFETs. 

 

The logic level I/Os are fine. DT pot resistance range 0k to 500k looks fine. VDSLVL pot looks fine since range is 0V-2.53V. 

MOSFET connections you described are correct. Make sure LSS connects back to GND if you are not using a shunt resistor. Motor current needs to dissipate to GND. 

Giorgio Valente said:

Do you think I can test the DRV8328ARUYR device with only the surrounding caps installed? 

The way I was thinking of testing it was to supply the device with 36V at the PVDD pin, then provide 3.3V to the SLEEP pin to awake the device and apply 3.3V to one of the gate drive input (INHx or INLx). Then, I would measure the voltage at the corresponding output (GHx or GLx). Do you think I can do that? Do you have any feedback on how to test it?

Before testing, please ensure you have these following things:

• Supply bulk capacitance on PVDD (usually 100s to 1000s of uF). The EVM has 780uF bulk capacitance on PVDD. 
  • If spinning a motor, you'll want to ensure that PVDD does not spike over 60V or else you could damage the PVDD pin. Supply bulk capacitance helps from the motor in overvoltage conditions
• I would perform in the following order:
  • PVDD = 36V
  • nSLEEP = 3.3V
  • Check to see if GVDD = ~12V. 
  • DRVOFF = 0V
  • Apply INHx/INLx = 3.3V/0V and see the GHx/GLx toggle accordingly with respect to SHx/LSS. High level input should yield ~12V on corresponding gate output with respect to source. 
  • If gate drive outputs do not toggle accordingly, check the nFAULT pin. 

Thanks,
Aaron

Hi Giorgio,

Giorgio Valente said:

Am I right in saying that the nFAULT pin cannot be left floating and a pull up resistor must be installed?

nFAULT is an open drain output, it requires an external pullup for the device to report faults through the nFAULT pin. I recommend R_nFAULT = 1kohm to 10kohm. 

Could you also ensure DRVOFF = 0V or tied to GND? 

Could you try INLA=3.3V and INHA=0V first, before INHA=3.3V and INLA=0V? Sometimes you need to charge the phase A bootstrap capacitor before turning on the high-side gate output. 

Can you share full schematic? Make sure there is a path from LSS to GND on your PCB, or else the VSEN_OCP may trigger. 

Thanks,
Aaron

Hi Giorgio, 

You're right, apologies on the DRVOFF comment, I forget that's only on DRV8328C/D. 

Giorgio Valente said:

Is this resistor always required? Even when connecting nFAULT to a uC? In the TI evaluation module DRV8328AEVM (see pdf of the schematic below) the nFAULT pin seems to be routed directly to the launchpad and to a status LED. There seems to be a pullup resistor (R16 in the schematic) but it's marked as DNP. 

Thanks for catching this! This was a mistake on the DRV8328AEVM, typically we recommend a 5.1kohm pullup for nFAULT to remain high since it is an open drain output. On the EVM, it is pulled up through the nFAULT LED, but I missed populating the 5.1kohm resistor. 

The EVM and hardware files are being updated to add the 5.1kohm pullup. This can be anywhere between 1k to 10kohm, this will just affect the RC time constant of nFAULT being pulled back up. 

Giorgio Valente said:

One question here, for INHA=0V, can I simply leave this pin floating or is it better to connect it to a power supply and apply ~0V? 

I would apply GND or 0V rather than leaving it floating to ensure that it stays pulled down to 0V. Internally there is a 100kohm pulldown resistor to GND but this is pretty weak. 

Giorgio Valente said:

Please see below the pdf of the power stage schematic. At the moment I've only installed U1 and the caps around it, R17, a 100kOhm pullup resistor instead of the LED2 (I'll replace this resistor with a smaller one, probably 1kOhm, depending on what I have available) and the current sensing resistor R18. R18 should assure a good path between LSS and GND.

Make sure R5 and R11 are populated so you actually turn on the MOSFET when toggling each input high. If these gate resistors are not connected, then the SHx voltages will not appear and recharge the bootstrap capacitor to provide the high side/low side gate voltage.

Thanks,
Aaron

Hi Giorgio,

I confirmed today that you need the gate resistors to see the gate driver output on the EVM. If they are not populated, nFAULT goes high, likely due to bootstrap undervoltage or GVDD undervoltage fault. 

Please populate R5, R11 and Q1, Q2.

Thanks,
Aaron