DRV8908-Q1EVM: DRV8908-Q1EVM

Hi,

Thank you for your question. IC Status is assigned as follows. I put example for C4. If DRV has some fault status, it reflect to IC Status. If fault status is changed, IC Status also changes.

In order to clear fault, CLR_FLT is the way. Write 01h at address 0x07h.

I suggest to set CLR_FLT first then check IC Status by sending some comment (read IC_STAT at 0x00h could be good one). 

regards

Shinya Morita

Hi ,

I am sorry  for the late reply .Thank  you  for your answer.   As you say ,I can use CLR_FLT to clear  fault .

Now ,I have 3 questions.

1.when system happen 2 errors (for example OCP and TSD) but the system is only that TSD  is disappeared , ,I need to set CLR_FLT to 1,the OCP error is not disappeared , right?

2. you say I suggest to set CLR_FLT first then check IC Status by sending some comment (read IC_STAT at 0x00h could be good one). 

Why I need to check IC Status? if the system did not recovery , the IC Status is not changed ,  right ?

3.I have disabled the openload ,why does status return a OLD fault when  I send control 1,2,4 channel output 1,3 channel output 0 ? 

my init register code:

InitSSP0_Drv8908();
initdataback = ReadOrSetSpiData( 0, CONFIG_CTRL_ADDR , (1<<1)|(1<<3)|(1<<0) , REG_WRITE_CMD );//0set 0 port overvoltage threshold is 33V,OCP not report FAULT pin

initdataback = ReadOrSetSpiData( 0, OLD_CTRL_1_ADDR , 0xff , REG_WRITE_CMD );//set 0 port disable all open load detection

initdataback = ReadOrSetSpiData( 0, OLD_CTRL_2_ADDR , 0xc0 , REG_WRITE_CMD );//set 0 port no report in nFAULT

initdataback = ReadOrSetSpiData( 0, OLD_CTRL_3_ADDR , 0 , REG_WRITE_CMD );//set 0 port disable all low-current open load detection

initdataback = ReadOrSetSpiData( 0, OLD_CTRL_4_ADDR , 0 , REG_WRITE_CMD );//set 0 port disable all low-current open load detection

initdataback = ReadOrSetSpiData( 0, OLD_CTRL_5_ADDR , 0 , REG_WRITE_CMD );//set 0 port disable all low-current open load detection

initdataback = ReadOrSetSpiData( 0, OLD_CTRL_6_ADDR , 0 , REG_WRITE_CMD );//set 0 port disable all low-current open load detection

why is  initdataback  0x00?????

my conctrol code:

     UINT16 spi_outdata= OutputPorts_drv8908(port,OP_CTRL_1_ADDR ,outdata );//OP_CTRL_1_ADDR 

why spi_outdata is 0xd19a?  I need to know  why is OLD true(My circuit is relaying, forming a bribe,no open load in the cicuit)? 

wait for your answer, thank you !

my macro definition:

#define IC_STAT_ADDR 0x00 //IC Status (IC_STAT) Register
#define OCP_STAT_1_ADDR 0x01 //Overcurrent Protection (OCP) Status 1 (OCP_STAT_1) Register
#define OCP_STAT_2_ADDR 0x02 //Overcurrent Protection (OCP) Status 2 (OCP_STAT_2) Register
#define OLD_STAT_1_ADDR 0x04 //Open-Load Detect (OLD) Status 1 (OLD_STAT_1) Register
#define OLD_STAT_2_ADDR 0x05 //Open-Load Detect (OLD) Status 2 (OLD_STAT_2) Register
#define OP_CTRL_1_ADDR 0x08 // OP_CTRL_1 //1-4 do pin
#define OP_CTRL_2_ADDR 0x09 // OP_CTRL_2 //5-8 do pin
#define CONFIG_CTRL_ADDR 0x07 //Configuration (CONFIG_CTRL) Register
#define OLD_CTRL_1_ADDR 0x1F //Open-Load Detect (OLD) Control 1
#define OLD_CTRL_2_ADDR 0x20 //Open-Load Detect (OLD) Control 2
#define OLD_CTRL_3_ADDR 0x21 //Open-Load Detect (OLD) Control 3
#define OLD_CTRL_4_ADDR 0x22 //Open-Load Detect (OLD) Control 4
#define OLD_CTRL_5_ADDR 0x23 //Open-Load Detect (OLD) Control 5
#define OLD_CTRL_6_ADDR 0x24 //Open-Load Detect (OLD) Control 6

Hi,

Thank you for your questions. 

1. Yes, need CLR_FLT to clear fault register. Fault registers are latched even if fault condition is removed.

Here is datasheet description- example for TSD.

2. By checking IC STAT, we can figure out what type of failure event happens. (Thermal, over current, OLD etc)

3. Need to disabled OLD before enabling output(address 0x08 and 0x09).

Or if you have nSLEEP=Low or VDD goes low, all register settings including OLD disabled(0x1F). Default setting for OLD_CTRL is "OLD enabled". FYI.

regards

Shinya Morita

hi  Morita

              Thank you  for you answer. I got it,beacuse nSLEEP=low, so OLD is enable. and my hardware aboard has some unexpect phenomenon.

            Now, I have another question. After nSLEEP  is  HIGH, i set register(address  0x07) to 0x0b and the VM is 24V ,, I enable output(address 0x08or 0x09) ,return data(OVP) have  over voltage  status,why?

           If I try to set register(address  0x07) ,  I enable output(address 0x08or 0x09) ,,return data have not this over voltage status,why?

hi  Morita

              Thank you  for you answer. I got it,beacuse nSLEEP=low, so OLD is enable. and my hardware aboard has some unexpect phenomenon.

            Now, I have another question. After nSLEEP  is  HIGH, i set register(address  0x07) to 0x0b and the VM is 24V ,, I enable output(address 0x08or 0x09) ,return data(OVP) have  over voltage  status,why?

           If I try to set register(address  0x07) to 0x0b again ,  I enable output(address 0x08or 0x09) ,,return data have not this over voltage status,why?

Hey Rita, 

Morita-san is out today and will get back to you within 1 business day (on Monday).  

Regards,

Jacob

Hi Rita san,

Thank you for your question. OVP default setting is 21V. VM 24V could be detected as OVP fault.

regards

Shinya Morita

hi Morita

          thank you for your answer. I have two questions.Please help me. thank you.

1.I know the OVP fault setting is 21V , so  I set register (address 0x07 ) to 0x0b , please see the picture, then I enable output(address 0x08 or 0x09 ),return data(OVP) have  over voltage  status,why?

but when I set this register(address  0x07) to 0x0b again , then I enable output(address 0x08 or 0x09 ),return data(OVP) have  not this over voltage status  status,why?

2. what does the bit OT in the SDO data  mean ? is bit OT represent OTSD and OTW in the IC status? in others word ,when bit OT is 1,  it show the chip has OTW or OTSD ,I need to check IC status  check the fault is OTW or OTSD?

thank you again.

hi  Morita

    I have third question . when I read IC status resigter, return data is OTW or OTSD setting 1, I need to check which channel happen OCP ? you can see the picture, if OTW or OTSD is 1, it show  Overcurrent is detected,so I need to check OCP_STAT_1 (address 0x01)or OCP_STAT_2(0x02) to find which channel is OCP? 

thank you again . Best wishes.

Rita,

This is a typo in the datasheet.  

The OTSD should read "Overtemperature shutdown is detected".

The OTW should read "Overtemperature warning is detected."

Regards,

Ryan

hi chips

          thank you for your answer. I have two questions.Please help me. thank you.

1.I know the OVP fault setting is 21V , so  I set register (address 0x07 ) to 0x0b , please see the picture, then I enable output(address 0x08 or 0x09 ),return data(OVP) have  over voltage  status,why?

but when I set this register(address  0x07) to 0x0b again , then I enable output(address 0x08 or 0x09 ),return data(OVP) have  not this over voltage status  status,why?

2. what does the bit OT in the SDO data  mean ? is bit OT represent OTSD and OTW in the IC status? in others word ,when bit OT is 1,  it show the chip has OTW or OTSD ,I need to check IC status  check the fault is OTW or OTSD?

thank you again.

Hi,

1)Normally if DRV detect OVP with 33V setting, should detect OVP with 21V as well.

Some proposal to debug.

- Read back IC Status (Addre4ss 0x00). It could be more direct way to check fault status. It may not be your case, but MCU/Firmware may miss understand on IC_STAT(Bit13-8) since it is unique format.

-Normally OVP may happens when bulk cap is too small and when motor stopped. Try to add bigger bulk cap (~200uF) between VM to GND for trial purpose.

2) Yes OT=1 means either OTW or OTSD. Need to read back 0x00 IC Status to identify.

regards

Shinya Morita

hi Morita,

     thank you for answer.  question 2 is ok ,thanks.

    But ,for answer one, I don't understand why DRV set 33v, need to check 21V as well, ?

    for your proposal, the return data in the SDO data is the same to IC_STAT , right ?  May  the return data in the SDO data(8-13bit) be different from IC_STAT(0-6bit) ?

    You mean ,any register( OP_CTRL_1  ,    OCP_STAT_2, OLD_CTRL_2    ,and so on  ) may miss or lose Bit13-8 in the return data,right?

    I should read IC_STAT and use this data (0-8bit)  to show DRV status,right?  

 the final question , when DRV is not sleep ,i set some registers to some value, but after, i set  DRV to sleep mode  ,  registers(I have setted) will recovery default value?

And when sleep is low, myMCU can  set any register(for example:address 0x08 or 0x09) to other value ? In other words, when sleep is low  and VM is 12V, I can frequently set register  to some other value ,once sleep is high , OUTPUT(1-8 channel) is vaule that I have setted lastest and other register is value that I have setted lastest,right?

    thanks.

Hi 

Thank you for your feedback. For 1),  IC_STAT(address 0x00) and SDO data (8-13bit) information should be same. However what you observed OVP was strange.  

>>but when I set this register(address  0x07) to 0x0b again , then I enable output(address 0x08 or 0x09 ),return data(OVP) have  not this over voltage status  status,why?

So I proposed to read IC_STAT(address 0x00) to double confirm.

When nSLEEP is Low, SPI interface is disabled and all registers back to default value. 

And tWAKE time(200us) exist. Need to wait 200us before SPI ready after nSLEEP L->H.

regards

Shinya Morita