DRV110: C_keep circuit under heat not working properly.

Dan Kisling

Part Number: DRV110

Hello support team,

I'm having an issue with the DRV110 in a system we recently designed.

We found that when our PCB was getting hot in the sun, the solenoids would no longer actuate. I increased C_keep from 1uF to 2uF and I was able to get the valve to actuate at high temperatures, but something didn't seem right so I did some additional analysis.

After some debug, I think I have found the cause - but it does point to a internal circuit in the DRV behaving quite strangely.

A few notes:

Issue is not solenoids heating up (we tested with solenoids in a heated chamber and saw no issue)
Issue happens at around 150 F (so this is well before the thermal shutdown in the chip. I have also confirmed that the status pin is LOW when EN is high)
CKeep = 2uF
RPeak = 68k
RHole = 68k
Rsense = 1Ohm
Rosc = 0 Ohm

Here is our circuit working normally at room temperature.

And here is our circuit at 150F. Note how the V_C_keep is not at 0mV when the EN pin goes HIGH. This will lead to a drastically shorter peak on time (50ms vs 200ms).

This significantly shortens the peak time and causes our circuit to stop working when hot. The chip is rated to 125C (257F) so I see no reason why the Keep pin should behave this way.

I was able to see this issue across multiple chips so I don't think this is a one off.

Any thoughts as to what is going wrong and ways to fix it?

Best regards,

Dan

over 2 years ago

0 Dan Kisling over 2 years ago

Prodigy 30 points

A few more breadcrumbs...

As I increase the temperature of the board slowly, you can see a sort of step function on the keep pin voltage:

Also you can see that the keep voltage is at zero just before the EN pin goes LOW and then very quickly raises to ~50mV.

Best regards,

Dan

0 Keerthivasan Kumanan over 2 years ago in reply to Dan Kisling

TI__Mastermind 18305 points

Hello Dan,

Can you send me a schematic and layout of the PCB. I strongly recommend getting our DRV110EVM and trying to see if this issue still occurs and to make sure this is truly a device issue and not a board or layout issue.

Best regards,

Keerthi Kumanan

0 Dan Kisling over 2 years ago in reply to Keerthivasan Kumanan

Prodigy 30 points

Hi Keerthi,
Schematic snippet below:

Layout snippet below:

Note that there are a lot of polygon pours here and I have them set to 50% transparency in Altium.

I do not have an EVM at the moment to try. I tried to follow the schematic to the datasheet as much as possible. The layout on the EVM seemed a bit convoluted, so I instead just followed best layout best practices and kept components close and mostly on the top layer.

Best regards,

Dan

0 Keerthivasan Kumanan over 2 years ago in reply to Dan Kisling

TI__Mastermind 18305 points

Hello Dan,

Can you measure the IC temperature as well and check for an undervoltage event?

Best regards,

Keerthi Kumanan

0 Dan Kisling over 2 years ago in reply to Keerthivasan Kumanan

Prodigy 30 points

Hi Keerthi,

VIN looks to be a solid 12VDC on the scope with no dips.

I cycled temperature a few more times with a thermocouple placed close to the component. Seems like that offset I'm seeing on KEEP appears at about 96C and disappears as it cools back down to 83C. Also interesting that the offset doesn't seem to increase very much with additional heat - it stays at about 50-60mV.

I ordered an EVM yesterday but it doesn't look like it has shipped yet.

I need to resolve this issue this week - so I may not be able to wait for the EVM to ship.

Best regards,

Dan

0 Keerthivasan Kumanan over 2 years ago in reply to Dan Kisling

TI__Mastermind 18305 points

Hello Dan,

Can you remove the Diode from the enable pin and check the waveforms.

Best regards,

Keerthi Kumanan

0 Dan Kisling over 2 years ago in reply to Keerthivasan Kumanan

Prodigy 30 points

Hi Keerthi,

I removed the LED on the EN pin and saw the same result. I don't see why that should have any affect, as I'm able to see that offset on the KEEP pin when EN is LOW.

At room temperature KEEP starts at 0mV and ramps to 100mV:

At ~100C KEEP starts from 60mV and ramps to 100mV which significantly shortens the time.

Dan

0 Jacob Thompson over 2 years ago in reply to Dan Kisling

TI__Mastermind 23411 points

Hey Dan,

Can you post a close up of the top of the chip on your board so we can read the markings on it? I will look into our systems to verify it isn't a counterfeit part. Did you buy it from the TI store on our website?

I recommend adding in a 500Ω current limiting resistor in series with VIN per 8.2.2.1 Current Limiting Resistor Selection.

Also you might want to try with a FET with a lower gate charge, like <10nC per this E2E post. "The typ DRV110 gate drive current is +/-15mA when Vin=15V, at lower Vin DRV 110 will have lower drivability. A FET with gate charge <=10nC is safe solution, depending on the application FET with gate charge greater than 10nC may work." Though yours at 20nC could work depending on your time rise and time fall requirements. Here's another E2E thread with thorough debugging attempts for this device, maybe reading through it will give you an idea.

Our team inherited the DRV110 from another group within TI so our design team is not familiar with this device. As a last attempt to understand this behavior, I recommend running a simulation in TINA (can find example schematic model in https://www.ti.com/product/DRV110#design-tools-simulation)

Regards,

Jacob

0 Dan Kisling over 2 years ago in reply to Jacob Thompson

Prodigy 30 points

Hi Jacob,

We had our board house buy these components so I would have to check with them on their sourcing. Here is a close up of the chip:

Those are very helpful notes on the current limiting resistor and the FET gate charge.

I understand your group may not be as familiar with this device. Is this behavior on the KEEP pin at higher temperatures expected or unexpected behavior?

Best regards,

Dan

0 Jacob Thompson over 2 years ago in reply to Dan Kisling

TI__Mastermind 23411 points

Hey Dan,

I confirmed the chip is legitimate, so that's good.

Unexpected, but I'll check with another team member just to see if he's seen this before.

Try the current limiting resistor on your board if you can, I'm interested to see if 500Ω or 1kΩ helps the issue or if it has no effect.

Regards,

Jacob

0 Dan Kisling over 1 year ago in reply to Jacob Thompson

Prodigy 30 points

Hi Jacob,

I did check this on the EVM and could not re-create the issue.

Then I replaced the DRV110 on the board with a new one ordered from Mouser and also was unable to re-create the issue. I can re-create the issue on all of the chips initially installed. So now I am less convinced the initial chip I had installed is indeed legitimate.

Best regards,

Dan