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DRV8316-Q1: What is the meaning of Device Fault Bit in IC_Status_Register Register?

Part Number: DRV8316-Q1

Tool/software:

hi,

I have a question about IC_Status_Register Register:

Scenario:

I don't have a motor hooked up, and after running for a while, the nFAULT IO is pulled low and the value of IC_Status_Register Register is read as 0X01, which means that only the Device Fault Bit is set.


Question 
1. what is the definition of Device Fault Bit, I didn't find it in the datasheet ?
2. whether Device Fault Bit represents a total fault, but other sub-faults are not set?

Thanks

  • Hi Owens, 

    Thank you for your question! 

    Can you help to clarify the status of the device when this fault occurs? When this fault occurs Is the device still commutating while there is no load connected?

    The IC_Status_Register Device Fault Bit is a catch-all flag when any fault is registered on the device. Can you read back the status registers again for IC_Status_Register, Status_Register_1, and Status_Register_2 to make sure no other fault/warning is transmitted? 

    Best Regards,

    -Joshua

  • hi,Joshua

       1. I tested it with load and hall disconnected.

       2. I added 3 status register lookups and I can see that only the IC_Status_Register Device Fault Bit is set, none of the other variables are set

  • Hi Owens,

    Thank you for the data.  

    When the device is reset through a reset pulse/fault clear bit, does this fault go away? If it is not able to be cleared it may be indicative of a broader device fault that may register on the device that does not fall into the fault status categories, such as a fault caused by DRVOFF. It may also be an issue in the reading of the registers, so can we confirm the proper addresses are being read? Experimentally you could trigger an undervoltage fault to observe if the registers are being read appropriately

    Does this fault trigger at any specific point during operation, or is it random? Can you also try using an actual BLDC motor to test with to observe device behavior? 

    Best Regards,

    -Joshua

  • Can you expand on the scenario where DRVOFF triggers a failure?Thanks

    Best Regards,

  • Hi Owens, 

    Yes - to the best of my understanding the DRVOFF function essentially acts as a latched fault where the power-stage is forced into hi-z, and this unique state (switching to and from) can result in the device registering a harmless fault that does not have an associated status register.

    And please let me know if you were able to follow-up on my previous reply's requests.

    Best Regards, 

    -Joshua