• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 30 subscribers
  • Views 271 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

DRV8316: Regarding SPI_FLT_REP setting

DRV8316: SPI Fault Reporting

Luke Oxley
Prodigy 20 points
Part Number: DRV8316

Tool/software:

Hello,

I am verifying fault handling functionality and would like to trigger a SPI fault. I have tried creating address and parity faults using the below methods.

SPI_ADDR_FLT
From the datasheet: 

"If an invalid address is provided in the ADDR field of the input SPI data on SDI, SPI address error is detected and SPI_ADDR_FLT bit in STAT2 is set. Invalid address is any address that is not defined in Register Map i.e. address not falling in the range of address 0x0 to 0xC."

I am periodically reading address 0x1D followed by reading STAT2, but do not see the SPI_ADDR_FLT bit latch.

SPI_PARITY

I am performing a read of STAT1 with an incorrect parity bit, but do not see SPI_PARITY set. However, I noticed in the datasheet this bit is marked with type "R-0".

I have cleared bit 1 of CR3 (SPI_FLT_REP, labeled as reserved in datasheet), but do not see nFAULT pin rise or SPI_FLT bit of IC_Status_Register set in either of the above cases.
Does the DRV8316 support SPI fault reporting?

  • 0
    TI__Genius 12231 points

    Hi Luke, 

    Please let me look into this SPI inquiry and follow-up within a day with a more detailed response after review.  

    Best Regards,

    -Joshua

  • 0 in reply to Joshua Maize
    TI__Genius 12231 points

    Hi Luke, 

    Luke Oxley said:

    Invalid address is any address that is not defined in Register Map i.e. address not falling in the range of address 0x0 to 0xC."

    I am periodically reading address 0x1D followed by reading STAT2, but do not see the SPI_ADDR_FLT bit latch.

    Can you observe if writing to instead of reading an address outside the 0x0 - 0xC range results in the fault bit being set?

    Regarding the parity bit test, can you help to provide the regsiter value you wrote to? 

    As long as the SPI_FLT_REP as you have confirmed,  then yes the DRV8316 should report on these failures.  If we can help to double-check the register valuesbyou have read and are writing to, that would be helpful to rule out any miscommunication. 

    Best Regards,

    -Joshua

  • 0 in reply to Joshua Maize
    Prodigy 20 points

    Hi Joshua,

    Thank you for the swift response.

    I have performed the same tests as noted above except with writing instead of reading and was able to observe successful reporting of both parity and address faults. 

    It appears the DRV8316 supports SPI fault reporting only for write transactions.



  • 0 in reply to Luke Oxley
    TI__Genius 12231 points

    Hi Luke, 

    Glad to have been of help resolving this matter. This observation will be a useful clarification going forward.  

    Thank You and Best Regards,

    -Joshua