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DRV201: DRV201 getting reset after read/write on i2c line

Part Number: DRV201

Tool/software:

Hi, 

I am facing the issue with DRV201-VCM where VCM position getting reset when we read VCM registers. I have update all the technical details in below case. Please let us know if there is any other information is required.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1436482/am62a7-using-drv201-vcm-driver-with-am62ax-processor

Regards,

Jay

  • Hi Jay,

    Thanks for your question.

    Can you please provide the byte stream sent to DRV201 for reading the VCM register. Also can you confirm if you were able to read any other register addresses?

    Thanks,

    Ibinu

  • Hi Ibinu, 

    Thank for your reply. 

    I am reading the VCM current registers "VCM_CURRENT_MSB" & "VCM_CURRENT_LSB". Yes, I am able to real all the 7 registers of DR201. I am using below command to get VCM position.

    i2cget -f -y -r 2 0x0e 0x03

    &

    i2cget -f -y -r 2 0x0e 0x04

    Let me know if any other details are required.

    Regards,

    Jay

  • Hi Jay,

    You mentioned in your previous post you mentioned, "We have observed that when there are too many transaction on the i2c bus on which drv201 is connected, we see SCL is pulled low for more than 0.5ms."

    Could you measure the DC voltage on SCL when sending these transactions? I want to make sure the DC level on SCL is above 0.63V and the device is not trying to enter SHUTDOWN mode while data is being sent. 

    Are you able to observe the RESET bit toggling when the device switches modes?

     

    Best,

    David

  • Hi David, 

    Thank you for your reply.

    Could you measure the DC voltage on SCL when sending these transactions? I want to make sure the DC level on SCL is above 0.63V and the device is not trying to enter SHUTDOWN mode while data is being sent. 

    Yes, we measured the DC voltage on the SCL line during the transactions. We observed that the DC voltage drops to 0V between read/write cycles, as shown in below image. During actual read/write operations, the SCL levels transition between 0V and 3.3V, following the clock signal.

    We have tried to read the RESET register parallelly when DR201 resets but haven't seen the RESET bit getting change and that could be due to "RESET
    bit is automatically cleared when written high." as per datasheet. 

    Let me know any other information required.

    Regards,

    Jay

  • Hi Jay,

    Is there any way you could use a o-scope to capture the I2C communication. This would give us more insight to the rise time and voltages of the signals. It could also be helpful to send the Salaea files (.sal) for use to look into. 

    Best,

    David

  • Hi David,

    I am Nisarg and working with Jay. we have captured the i2c signals (i2c clock and data) using Saleae-device and attaching the ".sal" file (.sal included in VCM_ISSUE_3_Final.zip file) along with this comment.

    VCM_ISSUE_3_Final.zip

    Using oscilloscope, Very hard to measure and capture the i2c-clk reset issue in time frame.

    For voltage level, we have attached below screenshot for i2c-2 clock and data voltage level. (Captured in Normal-Condition)

    Thanks,

    Nisarg

  • Hi Nisarg,

    Please allow me some time to review this file. I'll reach out soon with an update. 

    Best,

    David

  • Hi Nisarg,

    Apologies for the late reply, but after reviewing the file I'm still not sure why the device is resetting.

    Were you able to make any progress on this issue on your end?

    Best,

    David