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Original question:

DRV8300: Protecting the gates from excessive Vgs

DRV8300DRGE-EVM: DRV8300D vs DRV8300N – Slew Rate Limit on SHx Pin (V_SHSL)

Mat1980
Intellectual 1260 points
Part Number: DRV8300DRGE-EVM

Tool/software:

Hi team,

I noticed that the DRV8300D has a recommended V_SHSL (slew rate on SHx pin) of 2 V/ns, while the DRV8300N allows up to 50 V/ns.

Can you kindly clarify:

  1. Is the 2 V/ns limit a hard constraint or just a recommendation?
  2. What are the risks or limitations if this value is exceeded?
  3. How much could slew rate be extended?

Thanks for your help!

Matthias

  • 0
    TI__Mastermind 26826 points

    Hi Matthias, 

    Thanks for your question! There are quite a few team members out of office this week with the holiday in the US, but we will aim to provide a response later this week or next week. I appreciate your patience!

    Regards,

    Anthony Lodi

  • 0 in reply to Anthony Lodi
    TI__Mastermind 23676 points

    Hey Matthias,

    1. Yes a hard constraint.

    2. If this is exceeded then we are operating outside of the device tolerance and it could result in damage to the predriver FETs inside the device,,(damage to gate and source pins of the driver)

    3. It should not be exceeded. Please use gate resistors to slow down the slew.

    Best,

    Akshay