DRV8301 SPI output data

Hi Atsushi

SPI outputs at N just shifts out the response to N-1 commend. From the datasheet, F0 should be the fault bit indicated the last SDI is less or more than 16bit. I will confirm this later.

Sorry for my previous confusing asserting. I just edited my words.

Thanks.

Wilson

Motor Application Team

Dear Wilson-san,

Thank you for your reply.

I have a question.

In the datasheet P18, If SDI is less than or more than 16bits, MSB of SDO will report 1.

Is this F0 bit, isn't it?

Usually, "F0" is N-1 command of SPI, but in the above case, is "F0" the fault bit?

Best regards,

Atsushi Yamauchi

Hi Atsushi

Sorry for my confusing explain, “F” should stands for Fault. I will give you clear answer after confirmd.

Thanks.

Wilson Zuo

Hi Atsushi

Confirmed. F0 is a fault report bit for the SPI communication. The reports function is just matching the description of Page 18.

F0 bit will report HIGH at following conditions:

1. Start SPI communication the first time after EN_GATE is set to HIGH.

2. In the last SPI communication, during nSCS LOW, the word sent to SDI (locked at falling edges of SCK) is more or less than 16 bits. Then the current SPI output cycle will start with F0 bit = 1.

Thanks.

Wilson Zuo

Motor Application Team

Dear Wilson-san,

Thank you for your reply.

The customer checked SPI communication.

The result is below ;

Address: 0x03

1. write: 0b00010101010 --> SDO: 0000000000000000
2. read --> SDO: only F0=1
3. write --> SDO: only 0x03
4. read --> SDO: 0000000000000000
5. write: 0b00010101010 --> SDO: Data 0b00010101010
6. read --> SDO: 0000000000000000

I attached the timing diagrams.

1. 

2.

3.

4. 

5. 

6. 

   D0：CLK

　D1：SDI

　D2：SDO

And they set EN_GATE and /SCS correctly.

Is this result correct?

Are there any errors?

Best regards,

Atsushi Yamauchi

Hi Atsushi

I did test about SPI, and let me explain what you see here.(The root cause of what you see should be hided behind your 6 waveforms)

I have duplicated your problem based on a hypothesis (SCS had a unwanted low pulse) and still need your confirm.

Your step 1: Based on your waveform, this should not be the first time write SPI after EN_GATE. Because the red (SDO) is not F0=1 which will happen at the first time writing. So, if it is not the first time write, at this frame, your SDO responed the 0x00h status register and all 0.

Your step 2: If every thing is normal, the step 2 should not be this way. Since your last cycle is right 16 bits, you should not get F0=1 during this Read cycle. (My hypothesis is that you may have an unwanted SCS low between step1 and step2. Becaue any SCS low pulse without SDI and CLK will be considered as a fault frame. I reproduce the same outputs as your waveform with such a SCS fault low pulse. Please confirm this by display SCS waveform also ).

Your step 3: If step 2 is normal, step 3 will shift in your current words(N) and shift out the response data you written the last time(N-2) based on your last Read command (N-1). But since step 2 is not valid. The response data is not the thing.

Your step 4: This is a correct Read command (N) . But it is response data will be active at next cycle (N+1).

Your step 5: Normal write, which shift in the current words and shift out the correct state written in step 1 based on the last Read command (step 4). Note that, if you do write cycle twice, the second time the response words will be the 0x00h state register.

Your step 6: A normal Read command. but you should do the Read or Write again in step 7, then, you will see the response word come out from SDO showing your written in at step 5.

So, you just need to catch the SCS fault hypothesis between step 1 and step 2. I believe you will find it.

Thanks.

Wilson Zuo

Motor Application Team

Dear Wilson-san,

Thank you for your reply.

Before step 1, they reset by EN_GATE (High - LOW -High) for 1s.

I don't think the cause for this problem. 

But does it have possibilities for this problem.

And I attached the file of the waveform with /SCS.

7607.DRV8301_NCS.pptx

Best regards,

Atsushi Yamauchi

Hi Atsushi

I did all the same 6 SPI steps as you mentioned in your last posts. If without the SCS low pulse hypothesis, I can't reproduce you problem. All SDO is well explained as the datasheet said. But if I insert a fault SCS low pulse (could be a noise), I can get the same results (abnormal) as your post.

So my suggestion is to do a test of the waveform of SCS, SCLK, SDI, SDO with a voltage probe instead a digital probe and monitor the whole 6 frames in your steps including the time between two frames. Watch if there is small low pulse on SCS or fault frame with non 16bit CLKs.

Thanks

Wilson Zuo