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DRV8412 single bridge current waveform deformation

Other Parts Discussed in Thread: DRV8412, DRV8824

Hi all,


I am developing a new board equipped with two DRV8412.
Each DRV is configured in Dual full bridge mode with OC latching.
Power supply voltages are set with the following values:
PVDD = +24Vdc properly bypassed
GVDD = +12Vdc obtained from a linear regulator supplyed with the same +24Vdc that is connected to PVDD
and properly bypassed.

Each full bridge drives a 750uH inductive load (the full board drives 4 inductive loads).

The load current control is based on a standard chopping technique; PWM frequency is set to 31KHz.

About the PCB layout, it has been developed following the guidelines present on datasheet. Both DRV8412 and their
circuitry have been placed close to the output connectors.

The problem I am seeing is that from bridge AB i get a clean current waveform; from bridge CD I get a "dirty" current waveform, as illustrated in the pictures attached. This happens on both the DRV8412 on the same board and on different boards.

Image1: current waveform obtained from bridge AB (on the left, the full waveform, on the right a detail).

Image2: current waveform obtained from bridge CD.

Can anyone suggest me where is the source of this behaviour and give me a suggestion on how to reduce or eliminate it?

Thanks a lot,
Sergio

  • Hi Sergio,

    If you haven't done so, please try the following:
    1) Swap the inductive loads from bridge AB to CD. Does the noisy current move to AB? If so, it is the inductive loads. Please look for extra capacitance on the load.
    2) Can you provide a schematic and layout? Is the bridge CD layout significantly different than the bridge AB layout?
  • Hi Rick,

    thank you for your quick reply.

    Here the answers to your questions:

    1) I have already tried to swap the loads but without any difference. The noisy current still come from bridge CD.

    I add some more details about the load I am trying to drive:

    the load is composed by an inductance about 330uH placed close to the board connector and it is connected by a 1.3m (1300millimeters) cable to the coil (that move a mechanical parts of the machine); the coil has a nominal inductance value about 420uH.

    2) about the layout, the two output channels (from bridge AB & CD) are quite similar, as you can see by the attached file.

    Here you find the schematic diagram about the first DRV8412. The second has the same schematic.

    DRV8412 power stage.pdf

    And here the power stage layout:

    DRW8412 power stage layout.pdf

    Best regards,

    Sergio

  • Hi Sergio,

    Thank you for the additional information. We have not found anything that is obvious, so it looks like more investigation is required. It was noted the OUT_D path appears to be different from the other traces.

    1) Do you have a TI DRV8412EVM? If so, have you tried running the loads on it? What were the results?
    2) Would you capture the voltages in addition to currents at the connectors? Is there any difference between bridge AB and CD?
    3) When swapping the good load onto CD, did you also disable the AB side? This may provide an additional clue.
    4) Can you confirm that the same current probe was used in both measurements? Although unlikely, we want to rule out equipment.
    5) Can you confirm that the current probe is placed on the load wire for both measurements?
    6) It appears the trace for OUT_D is different than the other outputs, using multiple layers to get to the connector. You might consider looking at it in more detail. If this is suspect, can you consider modifying a board by cutting the existing path and wiring directly from the pin to the inductor on one board?
  • Hi Rick,

    thank you for your help.

    At this moment I can give you an immediate feedback only for some of your questions.

    Q1) Do you have a TI DRV8412EVM? If so, have you tried running the loads on it? What were the results?

    A1) I haven't tested the load on a 8412 demo. We have already used the DRV8412 on older projects without any problem,

    so I skipped this step. Usually we ask demo board only for never used devices.

    I think that we can perform some intermediate steps before test the load on a demo but I agree with the idea.


    Q2) Would you capture the voltages in addition to currents at the connectors? Is there any difference between bridge AB and CD?

    A2) I haven't captured the voltages on the load yet, but I think I can get some measurement soon.


    Q3) When swapping the good load onto CD, did you also disable the AB side? This may provide an additional clue.

    A3) No, the AB bridge was ON. I add that the two "current commands" in the two loads do not start (and finish) exactly

    at the same time, but they can be time shifted, depending on the machine commands.

    I will do this test as soon as possible.


    Q4) Can you confirm that the same current probe was used in both measurements? Although unlikely, we want to rule out equipment.
    Q5) Can you confirm that the current probe is placed on the load wire for both measurements?

    A4/A5) Same current probe used, properly degaussed and reset to zero, same scope. Probe connected to the corresponding load wire under test.


    Q6) It appears the trace for OUT_D is different than the other outputs, using multiple layers to get to the connector. You might consider looking at it in more detail. If this is suspect, can you consider modifying a board by cutting the existing path and wiring directly from the pin to the inductor on one board?

    A6) I strongly agree with your suspect on OUT_D trace. I will do what you suggest ASAP, and I will report the results.

    Thanks for all, have a nice day,

    Sergio

  • Hi Rick,

    I have some more news to report.

    Yesterday I managed to obtain a board to test in laboratory, not on the field.

    I set up the board with the same loads, same cable, same power supply and same additional inductors (placed on a little PCB with the same connectrors of the DRV8412 Driver board).

    Sadly I have to report that on this board, the ringing current is swapped on the AB bridge, on both the DRV8412; to be clear where we have the "good" layout side, where the PCB traces run always on top layer.

    Following your questions, I got this results:

    Q2) output voltages

    On output connector I saw a square wave (from 0V to +24V) with an overshoot on the "corners" with a maximum amplitude amplitude around 2.2V (see the following picture).

    Observing the same voltage signal on the DRV8412 pin I see a reduced overshoot amplitude. I think the ferrite L10 is doing its duty.

    Moreover, this also means that the problem comes from outside to the DRV.

    Q3) enable one bridge per time

    I managed to activate one bridge separately from the other. What I see is that the activation of the second bridge increase the current ringing on the first.

    Q6) PCB traces

    I cut the connection on the bottom layet on the CD bridge and replaced it with a short pice of large diameter wire; I expected to see the DC bridge current getting whorse, similar to the AB bridge current.

    On the contrary, The current shapes on AB bridge (dirty) and CD bridge (clean) stay the same.

    After this I concentrated my attention on the cable harness. Here I summarize the results of multiple tests:

    1A) machine cable + external inductors (330uH) + AB channel on -> peak to peak current ripple on AB out = 260mA

    1B) machine cable + external inductors (330uH) + AB and DC channel on -> peak to peak current ripple on AB out = 340mA (as previously said)

    2A) short and separate wire cable + external ind (330uH) + AB channel on -> peak to peak current ripple on AB out = 80mA

    2B) short and separate wire cable + external ind (330uH) + AB and DC channel on -> peak to peak current ripple on AB out = 80mA

    3A) long and separate wire cable + external ind (330uH) + AB channel on -> peak to peak current ripple on AB out = 118mA

    3B) long and separate wire cable + external ind (330uH) + AB and DC channel on -> peak to peak current ripple on AB out = 124mA

    this means that the lenght increase the problem

    4A) long and grouped wire cable + external ind (330uH) + AB channel on -> peak to peak current ripple on AB out = 309mA

    4B) long and grouped wire cable + external ind (330uH) + AB and DC channel on -> peak to peak current ripple on AB out = 437mA

    (worst case)

    5A) long and twisted wire cable + external ind (330uH) + AB channel on -> peak to peak current ripple on AB out = 118mA

    5B) long and twisted wire cable + external ind (330uH) + AB and DC channel on -> peak to peak current ripple on AB out = 118mA

    (best case)

    6A) long and twisted wire cable ( AB & CD wires grouped)  + external ind (330uH) + AB channel on -> peak to peak current ripple on AB out = 158mA

    6B) long and twisted wire cable ( AB & CD wires grouped) + external ind (330uH) + AB and DC channel on -> peak to peak current ripple on AB out = 189mA

    (intermediate case)

    7A) long and twisted wire cable ( AB & CD wires grouped)  + external ind (330uH) with inverted channels + AB channel on -> peak to peak current ripple on AB out = 77mA

    7B) long and twisted wire cable ( AB & CD wires grouped) + external ind (330uH) with inverted channels + AB and DC channel on -> peak to peak current ripple on AB out = 193mA

    (PROBLEM SWAPPED ON CD BRIDGE, like the boards on the field).

    I think we can conclude thath the cause is the harness.

    Let me know if you have some suggestions.

    Have a nice day,

    Sergio

  • Hi Sergio,

    Thank you for such a thorough evaluation, and narrowing down the cause to the harness.

    I will contact a colleague who has more experience dealing with longer cables and have him reply. It may be a couple of days.
  • Hi Rick,

    glad to read your words.

    I have prepared a table where I have summarized my test's results. I hope it will be useful.

    DRV8412 cable tests.pdf

    Apart from the harness effects, I think now remains only one point to clarify: why the activation of the secon bridge increases the current deformation on the first bridge. Let me know what do you think about it.

    Thank you for your kind help,

  • Hi Sergio

    Thanks of your great test summary on this topic. I have some experience on the spikes induced by the parasitic capacitance load, in which it could be more serious with long wires.

    Please refer to the following test.

    1.  DRV8824 (Actually it dosen't matter what the driver is) drives a big inductance solenoid.

    2. Drives a mid inductance stepper

    3. Drives a small inductance motor (0.5mH)

    Then, just add a 2nF cap in parallel with the small inductance motor and redo test 3 with exactly the same settings. We get the following result.

    The waveform we seen may caused by the quick charge and discharge current during the PWM edge.

    The spike should be no bad effect to the motor running.

  • Hello Wilson,


    thank you for your contribution.


    I ask you some more details about your experience; did you see the spikes on both motor windings or I suppose you seen it only on the windings with the capacitor in parallel?


    Moreover, you solved removing the capacitor? in my case I haven't a real capacitor, so I can't walk this way.

    I add a schematics of the loads I have to drive:

    loads.pdf


    Another important aspect of my case is that the presence of the deformation increases the peak current value and the RMS current value; this means that I have a misalignment respect the clean channel behaviour. The microcontroller sets the same current level (setting a 4 channels SPI controlled DAC) in the 4 output channels, but I get two channels with increased RMS current values and two channels with a lower RMS current.


    In my application is crucial to have a RMS and Peak current values as close each others as possible.

    Today I perform the characterization of the 4 channels, with the different types of cable and I'll post the numeric results as soon as possible.

    Thanks a lot for your kind help,

    Sergio

  • Here I report a table with the results of six measurement, all accomplished in the same way:

    - one channel (one full bridge) activated and the other three deactivated.

    - short and twisted cable (in this way I reduce the cable influence at minimum).

    - identical inductive load used on all channels.

    I have reset the board between a measure and the next.

    test A test B test C test D test E test F max diff on same channel
    Channel DAC value Imax [mA] Irms [mA] Imax [mA] Irms [mA] Imax [mA] Irms [mA] Imax [mA] Irms [mA] Imax [mA] Irms [mA] Imax [mA] Irms [mA] ΔImax [mA] ΔIrms [mA]
      300 775 702 910 741 834 670 872 708 845 683 837 674 135 71
    ch1 500 961 763 1087 895 1022 828 1052 869 1016 831 1012 826 126 132
      700 1174 951 1274 1062 1219 1004 1242 1036 1195 991 1216 1010 100 111
      300 861 690 897 731 834 676 833 669 855 694 802 640 95 91
    ch2 500 1038 844 1098 901 1033 839 1013 828 1035 848 1001 815 97 86
      700 1127 1009 1273 1067 1221 1010 1199 995 1233 1035 1202 1000 146 72
      300 928 753 946 771 936 762 863 696 932 765 886 718 83 75
    ch3 500 1104 905 1130 934 1121 925 1035 845 1106 919 1064 876 95 89
      700 1275 1059 1302 1090 1297 1084 1205 998 1283 1079 1252 1045 97 92
      300 818 641 932 758 943 769 852 683 885 718 877 710 125 128
    ch4 500 1005 802 1126 929 1136 938 1030 836 1076 886 1061 873 131 136
      700 1213 990 1309 1095 1314 1101 1230 1019 1269 1064 1257 1049 101 111
    max diff between channels max diff between channels max diff between channels max diff between channels max diff between channels max diff between channels
    ΔImax [mA] ΔIrms [mA] ΔImax [mA] ΔIrms [mA] ΔImax [mA] ΔIrms [mA] ΔImax [mA] ΔIrms [mA] ΔImax [mA] ΔIrms [mA] ΔImax [mA] ΔIrms [mA]
    300 153 112 49 40 109 99 39 39 87 82 84 78
    500 143 142 43 39 114 110 39 41 90 88 63 61
    700 148 108 36 33 95 97 43 41 88 88 55 49