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Original question:

DRV3245Q-Q1: SPI faults: clk and addr. Looks fine on oscope.

DRV3245Q-Q1: SPI faults: clk and addr. Looks fine on oscope.

Youyup Kim
Prodigy 25 points
Part Number: DRV3245Q-Q1

Hello. 

I have a similar problem with this problem.

SDO, Clock, and CSN signals are all output normally.

However, when the IC Status2 (0x0D) register is read, the SPI_CLK_FAULT value is set to 1.

(The SPI clock is set to 1Mhz.)

I wonder how the existing problems are resolved.

Could you let me know?

  • 0
    TI__Intellectual 2595 points
    Hello,

    The DRV3245Q-Q1 is designed and intended for customers developing automotive functional safety applications. As such, the device datasheet is covered under NDA, and we cannot discuss datasheet information in this thread. I've sent you a friend request on e2e, if you can please accept the request I will be able to PM you directly to help figure out the issue.

    Thanks,
    Garrett
  • 0 in reply to Garrett Walker
    Prodigy 25 points

    Hello,

    Thank you for your reply.
    And I accept your request(e2e).

    I have SPI CLK fault issue.
    My test process for the DRV3245 is as follows::
    [SPI Setting]
    - Clock Polarity(CPOL) is LOW(0b) & Clock phase(CPHA) 1b.(As described in the manual.)
    - SPI Baud is 1Mhz.
    [Test Sequence]
    1. I send 0x8800 :: Read cmd(bit15::1b) + IC Status 0 Addr(0x01=0001b) => Receive 0x400(FAULT)
    2. I send 0xEC00 :: Read cmd(bit15::1b) + IC Status 2 Addr(0x0d= 1101b) + 100b => receive 0x10

    Please let me know if you need more information.

    Thanks,
    Youyup