DRV8711: DRV8711 FET driver damage

Michal,

I found you asked the question to Rick after spending time on your test waveform and post. This is an e2e forum. So, let me put my comments here and hope that can explain the test waveforms.

1. The FET's gate voltage rising time is different than the output rising time. The output rising time (FET's miller plateau time) is partial of the FET's gate voltage rising time.

2. TDRIVE > 2 × RT; this RT is talking about the FET's gate voltage rising time. So, it is longer than 200ns.

3. "Is it possible that switching off the pre-driver before reaching full gate voltage could cause a gradual degradation of the DRV8711 gate holding current source?" If TDRIVE setting is short, IDRIVE is off before the FET's gate voltage is fully charged up, you can see the gate voltage may not reach its full range.

Wang Li,

Thank you for your reply.
I fully understand what you write. However, I do not know whether this could cause damage the DRV8711 (for example, by overloading the gate holding current source). In the device within about 1 to 3 years, DRV8711 is damaged and we are looking for the cause.
Of course, we adjust the parameter. However, we do not know whether this will solve the DRV8711 failure rate or whether we should continue to look for a problem in the HW.

Best Regards,

Michal

Michal,

Do you send the damage part to do the failure analysis? I want to know which pin get the damage. Also, when DRV8711 was damaged, did the external FET also get damage?

Would you like to send us the schematic to check if any potential risk? For example: does the design have enough input capacitance to absorb  the back drive energy...

Wang Li,

About this defect, I only communicated with Rick Duncan in this forum. We did not send the destroyed part to failure analysis.

Damage only occurs on pins A1HS, A2HS, B1HS, B2HS.
Usually only one of these outputs is damaged – any.
Multiple of these pins at the same time are damaged less frequently. However, this may be related to an attempt to restart the engine after a failure without limiting the number of attempts.

Usually no FET or any other component is damaged, only DRV8711.

The drv and power scheme:

The board is powered from a 43V / 3A stabilized switched power supply placed outside the PCB. The 43V power supply is connected to the PCB via XC18, XC19.
The input capacitor 100uF, 100uF near DRV8711, 100uF near bridge A and 100uF near bridge B (total 400uF low ESR on board) are connected at VM level. With the engine running, I checked the ripple at VM level, but there was no ripple or spike.

Best Regards,

Michal

Michal,

I cannot directly tell why A1HS, A2HS, B1HS, B2HS pins get damage. But, I have some questions:

1. DRV8711 is a 60V device with 52V recommended operating maximum input voltage. The input on the schematic is 48V. Does it power from a battery? What is the 48V input voltage range?

2. When the input source is hot plug-in, what is the maximum voltage spike can be found near DRV8711 input?

3. The 33ohm gate drive series resistor seems not necessary and 33ohm seems too high. Why are they put them there?

Hi Michal,

The reason for spikes is probably not very good decoupling of Vcc. I think there is no need for R53/R54, I would use MLCC 100nF/100V between

Vcc and GND at each HS Mosfet. With 2-sided board it would be difficult to reduce these spikes significantly.

I would also add for trial electrolytic capacitor 2200 - 4700 uF/63V at Vcc in case of overvoltage caused by motor resonance or braking.

DRV8711 is 60V max and it would fail first before Mosfets rated at 80V in case of overvoltage.

Best Regards,

Grzegorz

Hi Wang,

I would keep LS gate resistors, as far I remember I used to have lots of troubles

before adding 56R LS gate resistors.

Best Regards,

Grzegorz

Michal,

I have been seeing similar issues with gate drives getting damaged and oscillations. although I haven't seen the A1HS voltage spikes you are seeing. My application is also 48v with very small gate charge Nexperia FETs. Unfortunately I haven't found any solutions to the issues yet. One thing I will note is on your other post (https://e2e.ti.com/support/motor-drivers/f/38/p/865237/3220762) you note that even with increased gate resistance you still get significant peaks in the various signals. I found a similar phenomena and it seems correlated to 45 degrees from the zero crossings in the current waveform. I also noticed it seems like it is a spurious deadtime only cycle in the PWM output.

Allen

Hello,

I am worry about the high gate series resistor would add a resistance between the gate and source at FET off stage. When the switching node is sharply changed from one voltage level to another voltage level, the FET may be turned on by the FET's Cgd coupling. Specially, the lower Cgs capacitance FET.

Hi Wang,

You are right, shoot - through may be the problem.

I decided to stick to CSD18531Q5A (the same as on DRV8711 EVM) not only because of their high current capability but also low Cgd to Cgs ratio.

Best Regards,

Grzegorz

Wang Li,

ad 1. We supply our board with a purchased stabilized switching power supply MEAN WELL RS-150-48 powered from 230V mains. The power supply has the possibility to adjust the voltage. In order to obtain a good thermal and voltage reserve for the DRV8711, we set the voltage to 43V. Note: The first samples of our PCBs were supplied with 48V and no problems with DRV8711 destruction were noted.

ad2. 43V power supply on and off while the motor is running:

ad3. In the development of our PCBs, occasional false APDF, BPDF failures and high EMI have occurred. By reducing the overrun speed by incorporating a 33ohm resistor in the gate, these problems have been eliminated. Today, I think the best resistance value is 82ohm for the FET used.

Best regards,

Michal

Michal,

"occasional false APDF, BPDF failures" I don't know what is the APDF or BPDF?

If 33ohm or 82 ohm can affect the EMI result, that means its affects the FET turn-on/off speed. That gives me the shoot through concern and the FET damage concern.

Wang Li,

APDF failure means Channel A predriver fault, bit 3 STATUS Register.

I expect the FET gate resistor to reduce turn-on / off speed and thus reduce peaks in the system. Of course, the capacitance Cgd, which can cause a shoot-through (as mentioned by Grzegorz) at a high resistor value in the gate, must be taken into account.

We reached the value of 33ohm 5 years ago when developing our PCB. Today I would use 82ohm for an even slower turn-on / off speed. At this value, the turn-off of the FET used should be reliable according to the measured waveforms and the minimum Vgs(th) graph. I dealt with the determination of the maximum safe value of the resistor in the gate and Dead time set, but I did not want to distract the search for the cause of the DRV8711 destruction. I did not measure the effect of 82ohm on EMI.

If I wanted to further reduce the turn-on / off speed, I could add a small capacity between the G and S pins of the FET (the transistor used has a small Ciss 675pF capacity, while the transistor used in the DRV8711 EVM has a Ciss 3200pF). This will slow down the gate voltage change and improve the Cgd to Cgs ratio. However, it is necessary to control the total turn-off time in relation to dead time.

Best regards,

Michal

Allen,

could you please elaborate on your remark:

„I found a similar phenomena and it seems correlated to 45 degrees from the zero crossings in the current waveform. I also noticed it seems like it is a spurious deadtime only cycle in the PWM output.“

Unfortunately, I do not fully understand the comment.

Best regards,

Michal

Michal,

I set my scope to trigger on a "large" negative voltage spike that occurs when the bridge switches, I deceased the trigger level until the frequency of the trigger was low and noticed that the negative voltage spike correlated with 45 degrees from the zero crossing in the current sign wave assuming a constant speed (See Figure 1). This measurement was done with a very long time base (say 100ms/div). I then zoomed in the time base to see the rise and fall of the bridge and gates and saw the noise was occurring on a cycle that lasted 850ns which is the same time as my dead time (See figure 2). The point labled noise in figure 1 is where the negative voltage spike happens in figure 2. Unfortunately I have been destroying many driver boards trying to understand this problem and don't have scope captures of the phenomenon.  I will try to get actual scope traces soon.

Figure 1

Figure 2

I also am worried about distracting from the DRV8711 destruction issue as opposed to the gate resistor debate. In the past week I have broken 4 boards where the DRV8711 has been destroyed. The design works in production with a high inductance motor but when we go to a lower inductance motor the boards have been experiencing more issues.

Allen,

Thank you for the explanation. I will try to measure the described behavior in our application.

Best regards,

Michal

Hi Michal,

I am trying recently to reduce sources of EMI in my prototype board that I was testing quite harsh for the last couple of months (no any problems during these tests).

I have 4-layer board with ground plane and very well decoupled Vcc, there are no significant spikes on Vcc during Mosfet switching.

However when I checked sense resistor and output ringing, the spikes are very similar to yours.

At sense resistor it spikes to around -2V, but between LS Mosfets sources and GND the spikes are around -6V.

I have only 60MHz oscilloscope so I think these values should be multiplied by around 1.5 - 2 times.

I am guessing it is caused by parasitic inductances between LS Mosfets sources and GND ie. inductances of traces and sense resistor (it happens just after

body diode recovery as you marked on your graph).

Spikes happen during positive and negative slopes of output voltage, during negative ones spikes are slightly smaller.

Conditions during measurements were: output rise/fall times around 80ns, current around 14A (Irms = 10A for microstepping), Vcc = 50V.

To limit these negative spikes I will try to place high speed schottky diodes between LS mosfet sources and GND (parasitic

inductance in that case should be reduced 2-3 times), but I need to get them first.

I found also a solution on edn.com webpage with schottky diodes between switch node (output) and GND (but then I would need bigger diodes).

If it does not work and I have problems with reliability in future I can try to reduce switching speeds (I can increase heat dissipation a bit).

Best Regards,

Grzegorz

Wang Li,

thank you for your suggestions. Is there any further information to be expected from TI support, or has everything been said?

Best regards,

Michal

Hi all,

Just a small update on my reduction of EMI sources ie. ringing.

This time I used 100MHz scope and 150MHz probe, conditions were the same as before.

Negative peak on sense resistor was around -5V (there is some inconsistency with my previous result) and

between motor output and ground it was around -8V at frequency around 100MHz.

After placing schottky diodes PMEG10020ELRX between LS Mosfet sources and ground plane, one diode

per H-bridge, peak at sense resistor dropped slightly to -4.5V but the one at motor output dropped to around -3.2V

(more than 2 times), frequency increased to around 110MHz. Adding output filter should limit this ringing

to some reasonably level.

Reduction of peak at switching node should give some additional safety margin to Mosfets and DRV8711.

I was thinking about placing schottky diodes between switching node and ground but that

could interfere with auto mixed decay that I use.

I think all measured voltages should be multiplied by around 1.5-1.7 times because of gear bandwidth.

Best Regards,

Grzegorz

Grzegorz,

Thank you for sharing the test result.