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DRV8320R: DRV8320R destroyed in harsh environment

Part Number: DRV8320R
Other Parts Discussed in Thread: DRV8320

Hi,

I built several motor controllers yet with the DRV8320R gate driver and until now i never had any problems.

In the current application, the input voltage may vary between +-5V and can change in several us (motor acts as a generator

and the chopper brakes it). On two controllers it destroyed me the gate driver and the low side MOSFET, possible because

of false error handling from my side (reset the DRV8320 after an error occured). The thing is, that there occur sometimes gate

errors  (GDF), which need a manual reset of the driver and I don't understand yet, why this gate errors occur. It comes up when the motor

acts as a generator with around 20A, the voltage still seems stable through the current chopper. 

So, what can I possibly do to prevent this GDF? Is it possible, that the charge pumpe comes to its limits and to reduce the maximum gate current may be a solution?

Further, should I add additional buffering to the gate driver for example with a schottky diode followed by a 100uF cap?

From the layout side, I spent a separate GND plane to prevent some latchup through high current. There is also a lot of buffering of the

VDRAIN supply. So far, I never had any problems of instability with this kind of design.

  • 20kHz PWM frequency
  • 1/2A gate drive current
  • 2xBSC019N06NSATMA1 MOSFETs (around 102nC gate charge) --> Are two MOSFETs in parallel a problem for the driver? 
  • 48V input voltage

  • Is it possible, that the charge pump is too weak in average? When I calculate the total average current:

    Iavg = Qtot x #MOSFET x fswitch = 51nC x 12 x 20kHz = 12.24mA, maybe through parasitic capacities the gate charge

    further increases an so the charge pump is at its limit.

    I have also seen [1], the clearance is fine in my design (8 mil) but the gate current is too huge with 1/2A probably. I will reduce to test to around 260/520mA.

    Further, a better buffering of the VM can lead to a bigger difference in SHx to VM, such that i probably will connect the controller with less buffering

    [1] https://e2e.ti.com/support/motor-drivers/f/38/p/695182/2565497#2565497

  • Sebastian,

    Thanks for posting on the MD forum!

    Could you share your schematic?

    I am assuming you are not using any series gate resistors.

    Each of your FETs has 11nC typical QGD which is the capacitance that the IDRIVE is charging and which controls the VDS slew rate of the output FETs.

    With 1A/2A IDRIVE the small gates are way over-driven which is likely why you are seeing these issues.

    Per the IDRIVE FAQ (https://e2e.ti.com/support/motor-drivers/f/38/t/796378) the calculation suggests using around 100mA maximum to drive 22nC (11nC each) for 200nS VDS rise time. 200nS is very fast so likely less is needed.

    One other thing to consider is that two FETs connected to the same gate line with no series resistance can cause the two FET gates to fight with each other as they will never be the exact same parametrically. For this reason we suggest a small series resistor for each FET gate right at the FET pins so that there is some isolation.

    I would turn the IDRIVE down to minimum first and check the VGS and VDS of all six FETs, you can post the plots here if you want us to review.

    Regards,

    -Adam