DRV8662: using DRV8662 with bread board not PCB

Hi Luis,

The reason I use the bread board is that I want to be familiar with the chip and master the usage of it. So I use bread board at first, as long as I am familiar with DRV8662 then I will change it to PCB. I just think the bread board could be changed easily compared with PCB.

Here is the attachment which is circuit I connect on the bread board, are you able to see it?

5074.diagram.pdf

And I see the link you send me, it could be helpful. But I still have some questions which is in the attachment below.

questions about PWM.pdf

Could you please tell me whether I made any mistakes in the first attachment (called diagram), and clear up my confusions in the second attachment (called the questions about PWM)?

Best wishes,

Boyuan Huang

Hi Luis,

Can the input PWM be a signal of 200Hz, amplitude 5V, and 50% duty cycle if I use the filter of  DRV8662EVM which the link is here:

https://www.ti.com/lit/ug/slou319b/slou319b.pdf#page=15

Best wishes,

Boyuan Huang

Hi Luis,

I use the diagram below,diagram new.pdf

I leave the -OUT and +OUT open circuit and use oscilloscope to test Pin -OUT and +OUT. The result is that there is no rising voltage, it is just a 0 voltage line.

At the same time, I also connect the Pin GND and PVDD, it shows a 25V voltage line. So where is the problem? Why I cannot get 200Vpp as I want?

Best wishes,

Boyuan Huang

Hi, Boyuan,

Could you add 0.1uF capacitors at the analog inputs as shown in the datasheet? They are required in order to generate the common-mode level at the input.

https://www.ti.com/lit/ds/symlink/drv8662.pdf#page=8

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,

I do add the 0.1uF capacitors at the analog inputs, but it still does not work. I also test the Pin  -OUT and +OUT using the oscilloscope, however it also shows a 0 voltage level line. Where is the problem? I cannot figure it out. 

I don't know whether the problem is the electronic components I use, so could you please tell me the 'Manufacturer Part' of the components you use?

Best wishes,

Boyuan Huang

Hi, Boyuan,

Please take a look at the EVM bill of materials in the EVM User's Guide:

https://www.ti.com/lit/ug/slou319b/slou319b.pdf#page=19

I noticed that the VDD supply can be lower than the GAIN pins (based on your schematic). Please ensure to have VDD at least at the same level of the GAIN pins. In addition, could you tell me the PVDD level when the EN pin is in high and in low states?

Thank you.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,

As your suggestion, I set VDD 5V and GAIN 4V. When  the EN pin is in high, PVDD is a ripple diagram and when  the EN pin is in low,  PVDD is 0V. How to solve this?

Best wishes,

Boyuan Huang

Hi, Boyuan,

Could you share a oscilloscope capture of PVDD and BST pins when you enable the device? PVDD should be 0V when the device is disabled as you correctly mentioned, but I would like to ensure that the level you are getting is correct when you enable it. In addition, what is the voltage level you see at OUT+ and OUT- when the EN pin is enabled and when it is disabled.

If the ripple is high, you can include another capacitor at PVDD. However, I would recommend to create a PCB design for this device. Since the DRV8662 is sensitive to the board parasitic capacitance, you may get bad performance if the layout guidelines are not followed.

Best regards,
Luis Fernando Rodríguez S.