TPS54394: Problems with SW signal in regulator. Final ripple too high at the output.

Adrián Pérez

Part Number: TPS54394

Hello,

I am working with TPS54394 and we are generating two 5V outputs from 12V input. In channel 1, the output ripple seems ok, however in channel 2 the ripple of 5V output is too high.

In both channels the average output value is 5V.

I have monitored the SW signal for both channels, in channel 1 SW seems ok, however in channel 2 is not ok, I attach image for both signals. The configuration values for capacitors, resistors and inductor is the same for both channels, as both must be 5V output.

SW signal for channel 1

SW signal in channel 1

SW signal for channel 2

SW signal for channel 2

Ripple in channel 1

Ripple in channel 2

Ripple in channel 2

I would like to know what I could debug in the design to try to solve this problem, or what could be the cause related to this strage effect.

Many thanks in advance.

Kind regards

Adrián

over 3 years ago

0 Miranda Gu over 3 years ago

TI__Genius 15547 points

ma zhao, could you help with this?

0 Zhao Ma over 3 years ago

TI__Genius 15135 points

Hi, Adrian

1. could you send me the schematic and layout files? the screenshot is okay.

2. What is the loading of Channel 2? it looks IC works in DCM, but the Channel 1 works in CCM.

3. How do you measure the output ripple? please use the smallest loop to probe the Vout ripple.

0 Adrián Pérez over 3 years ago

Prodigy 10 points

Hi Zhao,

Many thanks for your response.

Here we attach the schematic for TPS54394.

In the schematic R155 and R156 are not mounted, and R252 and R259 are mounted to enable both regulators when 12v are ready.

Although output of channel 2 is called VDD_3V3, it has been configured for 5V output.

5287.SCHEM.pdf

0 Adrián Pérez over 3 years ago in reply to Zhao Ma

Prodigy 10 points

Hi Zhao,

Here we attach the layout screenshots for the regulator.

SCHEM_AND_PCB.zip

Please let me know if something is not shown correctly.

Many thanks and kind regards

Adrián

0 Adrián Pérez over 3 years ago in reply to Zhao Ma

Prodigy 10 points

Hi Zhao,

The loading of channel 2 is a voltage enabler with a linear regulator after it that gives 3v3 volts from the 5v input. The circuits powered by this 3v3 regulator are a small microcontroller and a camera chip.

I am going to check again the ripple with your recommendation.

Many thanks

0 Adrián Pérez over 3 years ago in reply to Zhao Ma

Prodigy 10 points

Hi Zhao,

I attach the ripple waveforms for both channels measured with the smallest loop.

Channel 1 ripple.

Channel 2 ripple.

kind regards

0 Zhao Ma over 3 years ago in reply to Adrián Pérez

TI__Genius 15135 points

Hi, Adrian

The schematic is okay.

But the layout is very bad, there is EVM reference layout, you can compare customer's layout with it.

1. the SW1/2 trace should be connected to inductor directly, not jump to another layer.

2. where are C231/C232 and C238/C240 be placed? they should be placed close to VIN1/2 pin.

From the customer's layout, you can see that SW1/2 trace is narrow and jumped to bottom layout, the trace has big parasitic R and inductor, which will cause big ripple on vout when loading is big.

So please improve the layout, then test again.