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UCC21750: TINA simulation error

Part Number: UCC21750
Other Parts Discussed in Thread: ISO5852S

Hello Andy, 

We got the TINA model from below E2E thread. 

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1005136/ucc21750-ucc21750?tisearch=e2e-sitesearch&keymatch=UCC21750%2520MODEL#

Above model operated well but my customer modified and added FET then the customer got a below error massage. 

What is the meaning of error massage "Component: U3.X_M47.M1"? 

I added the customer TSC file. please review it and let me know your opinion. 

UCC21750_211006.TSC

Thank you. 

  • Dino, 

    For a halfbridge, you want to make sure the highside FET is referenced to SOURCE of highside fet. in your simulation setup it was connected to the same ground as the lowside FET, I fixed it in mine as below. 

    This simulation was failing at only few ns which suggested that it was related to initial condition estimation., 

    For initial condition, there can be issues sometimes when TINA tries to calculate IC in this config. I believe its due to the inductor current-voltage relationship but I'm not exactly sure, to be honest. 

    So i changed IC condition to zero, but if you want to place initial conditions in the circuit you can try the 2nd option as well. 

    After this, i was able to run the simulation successfully. 

    Please follow these steps and if there are any further issues, dont hesitate to reach out to us. 

    If this has answered your question, please let me know by pressing the green button. 

    Best

    Dimitri

  • Hello Dimitri, 

    Very appreciate for your help. there are further questions.

    1. What is the meaning of error massage "Component: U3.X_M47.M1"?  . Does "U3.X_M47.M1" have any specific meaning? From this error massage, how can we start to debug? 

    2. As your recommendation, we can see above simulation result. please review below question and let me know your opinion. 

         - Why the gate waveform does not toggle even though changing input signal?

         - Is it due to the inductor current-voltage relationship you mentioned? or Schematic error?

         - If the inductor current-voltage relationship is cause of this, which inductor are you talking about? 

    Please let me know your opinion. 

    Thank you. 

  • Hi Nam, 

    1. What is the meaning of error massage "Component: U3.X_M47.M1"?  . Does "U3.X_M47.M1" have any specific meaning? From this error massage, how can we start to debug? 

    It means it had problem with some transistor inside the U3 model. This log gives virtually no information so all we know is that the simualtor ran into issue with that specific component. 

         - Why the gate waveform does not toggle even though changing input signal?

    Tie IN+ to RST pin or add a toggle off rst a few us into the simulation, then gate drive outputs. 

         - Is it due to the inductor current-voltage relationship you mentioned? or Schematic error?

    Usually my first test with halfbridge simulation issues is to remove the FETs/IGBTs and inductor and see if it runs. 99% of the time this is the problem. I do not have a lot of SPICE experience to give you a concise reason but it always seems to have to do with initial condition. 

    The other common issue is grounding between high and low side, or even primary-secondary. 

         - If the inductor current-voltage relationship is cause of this, which inductor are you talking about? 

    Connected between Mid and VBUS. 

    If possible I suggest to try this simulation in PSPICE for TI, I have a somewhat more confidence in that tool.

    Best

    Dimitri

  • Hi Dimitri, 

    Thank you for your kind explanation. one more question regarding below. 

         - Why the gate waveform does not toggle even though changing input signal?

    Tie IN+ to RST pin or add a toggle off rst a few us into the simulation, then gate drive outputs.

    => After Tied IN+ to RST pin, the gate waveform did not toggle(always high status). Did you try it? Is it operated? 

    Please review it again and let me know your opinion. 

    Thank you. 

  • Due to the RC time constant, it actually takes around 20us for RDY to go high, as VDD creeps up. 

    I removed both mosfet models and resimulated 

    UCC21750_211006 (3).TSC

    Unfortunately, convergence error happens the moment either of the devices turn on when reconfigured in halfbridge. This doesn't seem to be due to be an issue with the FET model, as I replaced it with built-in model from TINA and still having the same issue. 

    After playing with some of the analysis options it runs fully i still am unable to simulate the halfbridge and I am not sure why. Could you let me know or share the FET model you are using, I will use that when simulating. 

    I will try again Monday, in the meantime I suggest to try this simulation in PSPICE for TI instead.

  • Hello Dimitri, 

    Thank you for your strong support. Please refer the below FET information. I attached datasheet and .lib file of FET. 

    C3M0032120J1 datasheet.pdf

    C3M0032120J1.lib

    Please try it again and let me know your opinion. 

    Thank you. 

  • Hello Dimitri, 

    When Can I get your test result? please let me know your opinion. 

    Thank you. 

  • Dino, 

    I will reply in about 15 minutes with an update, and it turns out another poster's issue was having an issue that turned out to be exactly related to your issue. 

  • Hi Dino, 

    I spent a lot of time trying to get this to work both in TINA and PSPICE.

    The issue seems to be a bug with the UCC21750 pspice model when it is "floating," such as in a half-bridge configuration.

    I explained a bit more in another thread here which appears to be the exact same issue. 

    I am going to double check this issue with my colleague tommorrow and provide next steps. I will give an update at that time. 

    If the model needs a bugfix, it will take some time and I can't guarantee an ETA, so If you need to work with this model on a time-sensitive basis, please check my work-around suggestion in this thread

    Best

    Dimitri

  • Hi Dimitri, 

    Thank you for your suggestion. I am sorry but I don't understand your suggestion.

    "I suggest a workaround by referencing both highside and low-side driver's COM pin to node 0 and using VCVS with gain of 1 on only the high-side's secondary-side pins and referencing that VCVS to the high-side source to "isolate them."

    Could you explain you suggestion again relating on our schematic you gave me 4 days ago? 

    Please let me know your opinion by tomorrow after discussing your colleague.  

    Thank you. 

  • Hi Dino, 

    I confirmed with colleague that there is an issue with the model working in highside. We will need to fix this. 

    In the meantime you could try my suggestion, use UCC21750 on highside only, or use ISO5852S model with a current booster circuit (i confirmed this model working). 

    I haven't had time to try simulating my workaround, but my suggestion looks like below in pspice. You would not be able to use connect DESAT or clamp, and the performance wont be exactly the same. 

    I am attaching the PSPICE test bench i was using to do all the testing in case you'd like to use it. It is currently populated with ISO5852S, and the wolfspeed FET you are using should already be added in there.

    JOLT_HB_DINO.zip

    SInce the model will need to be fixed, I cannot provide a definite ETA this would be completed. So i can only suggest workaround options in the interim.

    Please let me know any other questions and it will reopen this thread. 

    If i have a chance to try the workaround circuit idea i shared above, I will update this thread. 

    Apologies that I can't provide a full resolution to the issue at this time. 

    Best

    Dimitri

  • Hi Dimitri, 

    Thank you for your support. 

    Pleas let me know UCC21750 update schedule when you fixed. 

    But one more question regarding ISO5852S. We are trying to import ISO5852S_TRANS.lib to TINA but there is an issue like below. 

    So I revised like below. Is it correct way for solving above issue? Will this affect performance of ISO5852S simulation?

    *.MODEL IGBT NIGBT
    *+ TAU=257.59E-9
    *+ KP=1.6467
    *+ AREA=8.0000E-6
    *+ AGD=3.2000E-6
    *+ WB=117.00E-6
    *+ VT=4.5775
    *+ MUN=3.2000E3
    *+ MUP=950
    *+ BVF=7.5320
    *+ KF=.5005
    *+ CGS=14.605E-9
    *+ COXD=13.357E-9
    *+ VTD=-5
    *$

    Would you recommend ref schematic of half-bridge  using  high side ISO5852S and low side UCC21750? 

    The customer want to check DESAT function in half-bridge configuration using TINA.

    I can't open the schematic you shared. I don't know reason, It seems to be my program problem. 

    Please let me know your opinion. 

    Thank you. 

  • Would you recommend ref schematic of half-bridge  using  high side ISO5852S and low side UCC21750? 

    This can work. And UCC21750 and ISO5852S have very similar DESAT circuit and timing. 

    So I revised like below. Is it correct way for solving above issue? Will this affect performance of ISO5852S simulation?

    This will not affect performance. 

    Best

    Dimitri

  • Hi Dimitri, 

    I am sorry to bother you but would you modify customer simulation schematic to operate as a half bridge configuration? 

    ISO5852-UCC21750_211015-1.TSC

    Thank you. 

  • Hi Dino, 

    Could you clarify what you need me to do?

     The schematic you shared is already in half bridge configuration and looks correct to me. 

    I would suggest add 200pF cap from DESAT pin to COM, but other than that it looks fine. 

    Have you installed PSPICE for TI (TI's free version of OrCad) before? If you haven't I would honestly suggest you to try that. 

    I am sorry to bother you

    No need to apologize. Its not a bother. Plus this is my job.

    Best

    Dimitri

  • Hi Dimitri, 

    Thank you for your kind support. 

    The schematic I shared above is not simulated well using TINA. 

    If I use calculate operating point option, The simulation is fail. I changed IC condition to zero, After this, I was able to run the simulation successfully. 

    But the gate waveform does not toggle even though changing input signal. I didn't find the reason of this error. 

    Would you try to simulate TINA model I shared above? 

    The customer said they can't use tool of PSPICE for TI. The reason why I am trying to simulated using TINA

    Please review it again and let me know your opinion. 

    Thank you. 

  • You may have to give the supplies and RST as PWL and let them ramp up. 

    I can give a tray later today. 

  • Hi Dimitri, 

    Did you try this simulation?

    I have tried this simulation as your recommendation but failed. Please let me know your opinion. 

    Thank you.

  • Hi Dimitri, 

    I am sorry to push you but Is there any update on this request? 

    The customer and I are not familiar with using PSPICE tool, so we are trying to simulate using TINA tool. 

    As mentioned before, I failed the simulation of half bridge configuration though using ISO5852S on hiside and UCC21750 on lowside. and I didn't find the reason. 

    Would you recommend reference circuit to simulate half bridge configuration using ISO5852S on hiside/UCC21750 on lowside and SICFET on TINA tool?

    If you can modify TSC file which I shared above, It is best option. 

    The first target of this simulation is driving SICFET and check DESAT function operation.

    Please let me know your opinion. 

    Thank you. 

  • Dino,

    I have not managed to get the simulation working in TINA. 

    I urge the customer to use PSPICE for TI in this case. 

    Best

    Dimitri

  • Hi Dimitri, 

    Thank you for your strong support. I understand your status. 

    As mentioned before, the customer and I am not familiar with PSPICE tool. I downloaded PSPICE for TI tool for the first time to support this case. There are some questions. 

    1. Do you mean you can't not support simulation model in TINA?. Is it because of the limitation of TINA tool itself or  Is it because it's efficient to use PSPICE?

    2. If the customer have to use PSPICE tool, they want to get a reference schematic to simulate half bridge configuration(Highside: ISO5852S, Lowside : UCC21750) and test simulation result.  In the previously shared data, the device is not visible in the circuit. Is it possible to support to this request? 

       => If we use PSPICE tool, Is it possible to check DESAT function?

    I am trying to simulate using PSPICE tool but If possible, could you support some simple guide how to simulate using PSPICE tool? 

    Thank you.  

  • 1. Do you mean you can't not support simulation model in TINA?. Is it because of the limitation of TINA tool itself or  Is it because it's efficient to use PSPICE?

    Our models are "supported" for TINA and PSPICE, but we only test with PSPICE. Generally there are no issues with TINA.

    Is it because it's efficient to use PSPICE?

    Yes. 

    2. If the customer have to use PSPICE tool, they want to get a reference schematic to simulate half bridge configuration(Highside: ISO5852S, Lowside : UCC21750) and test simulation result.  In the previously shared data, the device is not visible in the circuit. Is it possible to support to this request? 

    We do not have an official half-bridge reference schematic.

    In the previously shared data, the device is not visible in the circuit.

    What do you mean by the gate driver is not visible ?

    You may have to scroll down a little bit below the circuit to see those.

    ISO5852S and UCC21750 have pinout differences, so i created netnames and placed ISO5852S "outside' the circuit, connecting everything with Netnames. Naming Nets the same thing connects them in the circuit. This just made it easier to quickly swap between components. 

       => If we use PSPICE tool, Is it possible to check DESAT function?

    Yes. 

    I am trying to simulate using PSPICE tool but If possible, could you support some simple guide how to simulate using PSPICE tool? 

    I can help here somewhat. There is also getting started guide from TI

    E2E also has a forum for support

    Best

    Dimitri

  • Hi Dimitri, 

    Thank you for your support. 

    I am going to ask a question about PSPICE simulation error using data which you shared before. 

    Can I keep using this thread or do I have to open new thread?  please let me know your opinion. 

    Q1] If i click green circle on schematic, i can see below warning massage. Can I ignore this warning to simulate this schematic? 

    " Warning(ORNET-1119) : The part/device cannot bot simulated, No PSpiceTemplate found on U8, ignoring this part/device from simulation netlist" 

    Q2] If i click view simulation results, I can see below simulation result. 

    But If click Run PSpice button, I can see below error massage, How can I debug this error, how can I run simulation to check other point?

    I am trying to study PSpice for TI using link you shared but Please help to solve this question. 

    Please let me know your opinion regarding above questions.

    Thank you.

  • Can I keep using this thread or do I have to open new thread?  please let me know your opinion. 

    Its OK to keep in this thread for now. 

    I think this issues has to do with the library files path. Can you try below steps:

    1) Pspice -> Edit Simulation Profile

    2) Go to Configuration Files -> Library

    For each model library it is crying about, go to Browse, Select that library in the test bench folder, click Add as Global OR Add to Design. Either one. 

    Let me know if this resolves your issue here. If not, would you please post a picture of the screen for configuration files like I did?

    Best

    Dimitri

  • Hi Dimitri, 

    I tried as your suggestion but There is issue on my PSPICE for TI. 

    If I click Edit simulation Profile like below, 

    The PSPICE for TI program crashed with below massage. I already post this issue on Simulation, hardware$system design tools- Internal forum.

    I think this is not your job but is there any suggestion to solve this issue? This case is related customer request. please let me know your opinion. 

    My program version is like below, How about your? 

    Thank you.

  • Dino, 

    That is error is strange. I am running the same version in Win10 and haven't ever had that before. 

    Would suggest to try to reinstall the program / seek help from the PSPICE forum, they are experts on this tool and can better support. 

    Best

    Dimitri

  • Hi Dimitri, 

    Thank you for your advice. 

    For my issue of shut down, I already requested to the PSPICE forum. 

    But in case of my customer side, There is same error related C3M0032120J1.lib as mentioned before post.

    So I recommended 'edit simulation profile' as your recommendation but there is still an issue. 

    Please refer to the below a picture of the screen for configuration files of customer. please review it and let me know your opinion. 

    Thank you. 

  • Hello Dino,

    Dimitri is out of the office at the moment but should respond to your recent questions within the next business day.

    Regards,

  • Dino,

    Try giving it the direct path for the C3M library. Delete that line by selecting it and pressing the weird looking X.

    Then select it again by clicking browse then add as global. It should show the complete path: (like "C:\Desktop\project\blah\C3Mxxxx.lib" rather than the relative path "./c3m.lib")

    Its possible that library is not in the same directory as the project, or in a different folder which might be causing this error.

    Let me know the result.

    Best

    Dimitri

  • Hello Dimitri, 

    As mentioned before, my program has some issue. I will recommend your solution to customer and let you know the result. 

    For clarify,  I would like to double check. Don't you have a problem to do simulate this? Below file is data you shared before. 

    8233.JOLT_HB_DINO.zip

    Please simulate it using this file and let me know your result whether there is same issue or not.  

    Thank you.

  • Hi Dino, 

    I downloaded your attached zip and opened  in PSPICE for TI, same version you are running,  rather than the full-fat version of OrCad.

    Initially get the same error. 

    I deleted C3M library from Config files, then readded again by going to Browse-> select the model in the trans folder-> Add as global. 

    After this, you probably got an error referring to "PSPICE detected something with diodes and allows maximum of 3 traces"

    When i was making the test bench in my fullfat version, i added many traces to the output. When we import external model PSPICE for TI complains because its the limitation of the free version. 

    Basically to fix this, just throw a current or voltage probe somewhere, anywhere as long as its connected to something and you will be able to run the simulation successfully after that. You can add the traces in the waveform window afterwards. 

    Let me know if any further questions. 

    Best

    Dimitri

  • Hi Dimitri,

    Thank you for your support on this issue. I noticed that the UCC21750 device has PSpice models and reference designs available on ti.com, but they are not included in PSpice for TI's built-in library. Could you please republish the model in order to add it to the PSpice for TI library? Feel free to reach out to me by email if you would like to discuss further.

    Thank you,

    Jackie

  • Jackie, we are aware of this too, but not sure when we will republish the model since there is some debug we need to do. 

    Is this an urgent need?

    Best

    DImitri

  • Hi Dimitri,

    Thank you for the additional information. There is no urgent need. 

    Thank you,

    Jackie