There have previously been threads about disabling the switching of the DRV pin however all of the options recommended creating a fake fault (over voltage, over current, etc) )which results "reset loop". This is undesirable for my application:
1. I want the controller to start switching immediately after I "enable" it.
2. I don't want to waste any unnecessary energy (charge and discharge the Vdd cap).
I was thinking of pulling the CS pin to an intermediate level ~ around 1V so that I am above the maximum threshold and every switching cycle I won't DRV the primary FET yet I will be below the OVCP so the controller won't discharge the Vdd capacitor.
Do you think this will work well? Anything I might be missing?
I can't test on my own yet, since I am awaiting the EVM..
