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UCC21750: UCC21750 Isolated Gate Drivers

CHOLOUX RUDY
Prodigy 20 points
Part Number: UCC21750

Hello,

We are currently using an UCC21750 driver on an application (Three phase inverter 400V 10kW).

On some condition (under analysis), the driver stop the PWM during approximately 1ms.

this behavior seems to resemble to a activation of the internal under voltage look up or activation of the short circuit protection.

 

C4  : Gate voltage with high rejection differential probe

C5  : Gate voltage with differential probe

C6 : DRV flag from all drivers with addition monitoring

C4  : Gate voltage with high rejection differential probe

C5  : FLT FLAG of UCC21750

C6 : RDY FLAG of UCC21750

When the driver stop, we observe an additional pulse on the gate voltage before the ‘long stop’ of the driver (tFLTMUTE or tRDYHLD).

Do you have any idea what can cause this behavior?

 

C5 and C6  : PMW_H and PMW_L input of driver

C4  : Gate voltage with high rejection differential probe

Other problem, the RDY flag is raised with VCC=3,3V and VDD=15V

Do you have any idea what can cause this behavior?

Many thank for your support.

  • 0
    TI__Genius 10652 points

    Choloux,

    CHOLOUX RUDY said:
    Other problem, the RDY flag is raised with VCC=3,3V and VDD=15V

    Could you clarify? It sounds like what youre saying is that when VCC=5V, there is no issue, but

    Or do you mean RDY flag is raised all the time at VCC=15V?

    CHOLOUX RUDY said:
    Do you have any idea what can cause this behavior?

    Could you provide scope shots for the following pins when RDY / FLT falls, measured at each pin.

    IN+/IN- (if in- grounded, no need to share)

    VDD

    VEE

    VCC

    DESAT

    RDY

    FLT

    Other questions?

    * Are you using Interlock for Input PWM? How much deadtime is given? If possible, zoomed in screen shot of input PWM hs and ls would be great.

    * Which driver trips RDY/FLT? HS or LS? Is it consistent?

    * It looks like this is happening at a specific duty cycle of HS

    * How are you probing input side signals? With probe and tip/pigtail? They are very noisy and this makes me wonder if there is false turn-on coupled by EMI which may be worse at low VCC due to reduced VIH level

    * Are GATEH and GATEL using the same probe? I assume not because GATEH is significantly more noisy but want ot check.

    Also it would be critical for us to see the schematic from driver to power switch and layout. We have seen layout/schematic directly cause this.

    We can share this privately thru e2e message or email.

    best

    dimitri

  • 0 in reply to dimitri james
    Prodigy 20 points

    Hi,

    dimitri james said:

    Could you clarify? It sounds like what youre saying is that when VCC=5V, there is no issue, but

    Or do you mean RDY flag is raised all the time at VCC=15V?

    RDY flag is raised all the time at VCC = 3,3V and VDD = 15V.

    dimitri james said:
    * Are you using Interlock for Input PWM? How much deadtime is given? If possible, zoomed in screen shot of input PWM hs and ls would be great.

    Yes Interlock is used. Deadtime = 200ns

    dimitri james said:
    * Which driver trips RDY/FLT? HS or LS? Is it consistent?

    HS and HL

    dimitri james said:
    * How are you probing input side signals? With probe and tip/pigtail? They are very noisy and this makes me wonder if there is false turn-on coupled by EMI which may be worse at low VCC due to reduced VIH level

    Each GATE with probe TIVP02 (Isolated Measurement Systems | Tektronix)

    Access to input signal is difficult on your application (integration issue) so, measurement of this signals (input side) are noisy (high level on noise between board GND and scope Earth).

    The encounter behaviour appear also when measurement of input side is not performed)

    The "noisy" Measurement has permits to conclude than the '1ms' stop for the driver is not due to your controller (DSP)

    When the driver stop, The APWM signal is low , then the RDY signal fall and sometime FLT input fall for a short time when RDY is low (see second figure (blue and orange signal)

    dimitri james said:
    * Are GATEH and GATEL using the same probe? I assume not because GATEH is significantly more noisy but want ot check.

    No, I used the probe TIVP02 (Isolated Measurement Systems | Tektronix) for each GATE.

    Thank for your assistance

    Regards

  • 0 in reply to CHOLOUX RUDY
    TI__Genius 10652 points

    Choloux, 

    APWM stops when RDY fall is detected, and the ~1ms hold off time is the ready hold off time. 

    The fact that this is happening at 3.3V makes me think there is noise coupled onto VCC from 

    My first suggestion would be to measure VCC, VDD, VEE and add additional bypass caps (using 2 caps -> 100nF + 2.2uF or greater, close to device pin <5mm)

    Can you share your schematic, and preferably layout? This will help a lot to see if there are any things which would exacerbate this type of issue. 

    Best

    Dimitri