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While Q1 is on, what is the maximum leakage current value IDSS that can occur in Q2 while it is in the off state before the output voltage is effected? My hope is to analyze any worst case scenario failures that this device can see, so even if this isn't likely I want to know the limit In the datasheet, IDSS is specified as having a maximum current of 1 uA when VDS = 24V, will any current above this change the output voltage?
Hello Connor,
Thanks for your interest in TI FETs. The change in output voltage due to the leakage current thru either of the FETs should negligible. The PWM controller should correct the duty cycle to maintain output voltage regulation irregardless of the leakage thru the FETs. I pulled up the characterization data collected during product development and IDSS for each of the FETs at VDS = 24V & TJ = 25°C is much less than the 1μA maximum spec in the datasheet. TI can only guarantee what is specified in the datasheet. Keep in mind, leakage increases with both temperature and voltage but still should have little or no effect on the output voltage. Please see the technical articles below for more details.
Best Regards,
John Wallace
TI FET Applications
Hi John,
Thank you for the response! This is very helpful and answers what I need to know for the CSD87381P.
I have the same question for the CSD875888N, is the answer the same as well?
Regards,
Connor
Hi Connor,
The CSD87588N uses different FETs that have a higher VGS rating: +/-20V vs. +10V/-8V for the CSD87381P. Both power block devices have the same maximum IDSS specified in their datasheets: 1μA at VDS = 24V & TJ = 25°C. The CSD87588N typical leakage is about the same magnitude (<50nA) based on the characterization data at VDS = 24V & TJ = 25°C. Let me know if you have any additional questions or need more information.
Thanks,
John