TPS51200: question to JEDEC's "Power-up initialization sequence"

Hi Team, 

JEDEC's「Power-up initialization sequence」 says DDR3 application needs to meet either ① or ②. 

But my understanding is TPS51200 don't meet ①, is it correct that if TPS51200 can meet ②, TPS51200 can be used in DDR3 application? 

①

• VDD and VDDQ are driven from a single power converter output, AND
• The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to

VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side.

In addition, VTT is limited to 0.95 V max once power ramp is finished, AND

• Vref tracks VDDQ/2.

➁

• Apply VDD without any slope reversal before or at the same time as VDDQ.
• Apply VDDQ without any slope reversal before or at the same time as VTT & Vref.
• The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to

VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side.

Thanks.

Regards,

Jo