LM5069: Design Review

Bhanu Indu Sekhar Muppalla

Intellectual 400 points

Part Number: LM5069

Hello TI Team,

I have designed LM5069 for OV and OC protection for a load supplied from a battery Li Ion.

Could you help me out by reviewing my design

/cfs-file/__key/communityserver-discussions-components-files/196/2021.60C_5F00_temp.xlsx

Also I have 5 questions

1) In the current limiter section what do you mean by minimum, typical, maximum current limit.

2) In startup section the startup time is 114.00 ms but the fault timeout is 0.47 ms. In the video it was mentioned that this would affect the device.

Could you kindly check the design and let me know if there is a problem

3) What is VDD connected connected to PGD

4) Also what do you mean by upper and lower threshold for UVLO and OVLO

5) I do not know my output load capacitance to accurately enter in operating condition sections, so what would be a good value ?

Thanks

over 3 years ago

+1 Rakesh over 3 years ago

TI__Guru** 105811 points

Hi Bhanu,

Design looks good.

1A) The current limit has accuracy. So, the minimum and maximum values defines the range of current limit considering accuracies

2A) If you Use External Soft-Start Control (dv/dt) method, the startup time can be longer than the fault timeout. In power limit mode operation, the fault timeout should be set higher than the startup time

3A) PGD is open drain output and should be pulled to external source to use the information.

4A) upper and lower threshold for UVLO and OVLO are rising and falling thresholds of Vin where these protections are active.

5A) Please add all the capacitance connected to the output of hot-swap as well as the input capacitance of the loads connected to the hot-swap output.

Best Regards,

Rakesh

0 Bhanu Indu Sekhar Muppalla over 3 years ago in reply to Rakesh

Intellectual 400 points

Hello Rakesh,

Will the current fault timeout and startup time work or do I need to change any values.

Also you mentioned

Rakesh said:
In power limit mode operation, the fault timeout should be set higher than the startup time

to achieve this where do I need to change the values in the design calculator

Thanks

+1 Rakesh over 3 years ago in reply to Bhanu Indu Sekhar Muppalla

TI__Guru** 105811 points

Hi Bhanu,

Will the current fault timeout and startup time work or do I need to change any values.

No need to change..

to achieve this where do I need to change the values in the design calculator

you can set F71 to No to use power limit mode of startup instead of dv/dt

Regards,

Rakesh

0 Bhanu Indu Sekhar Muppalla over 3 years ago in reply to Rakesh

Intellectual 400 points

Hello Rakesh,

If I do not need PGD information can I leave it unconnected?

Also Vdd is the output from PGD right?

What should the clamping voltage be for the TVS diode at Vin and should the TVS diode be unidirectional or bidirectional

Thanks

0 Rakesh over 3 years ago in reply to Bhanu Indu Sekhar Muppalla

TI__Guru** 105811 points

Hi Bhanu,

PGD can be left OPEN if unused.

You can pull-up PGD to Vout through a resistor if low voltage supply VDD is not available in your system

For your specs unidirectional TVS diode SMCJ60A should be good enough. Please refer https://e2e.ti.com/blogs_/b/powerhouse/posts/selecting-tvs-diodes-in-hot-swap-and-oring-applications article for more information.

0 Bhanu Indu Sekhar Muppalla over 3 years ago in reply to Rakesh

Intellectual 400 points

Hello Rakesh,

What should the value of Cout be for lm5069 and should it be ceramic or electrolytic

Thanks

0 Rakesh over 3 years ago in reply to Bhanu Indu Sekhar Muppalla

TI__Guru** 105811 points

minimum 1uF ceramic output capacitor is needed. Additional cap can be used based on your load filtering requirements

Power management

Power management forum

LM5069: Design Review