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Hi Power Team,
I'm confused about figure 2 in application report SLUA923. Figure 1 shows upper Mosfet as Q1 and lower as Q2. Figure 2 and other places throughout the report show Vsw node low when Q1 gate is high. Shows Vsw node at V+ when Q2 gate is high.
I believe the notations for Q1g and Q2g are swapped.
Regards,
Stuart
Hi Stuart,
You are correct. Those two gate signal names should be swapped.
Regards
Manikanta p