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UCC28180: Power management forum

Part Number: UCC28180
Other Parts Discussed in Thread: UC3854B, UC2854B

Hello all,

A long time ago: I asked a very similar question, at an earlier time in our project. At that time, we thought we resolved the issue, but turns out, it still needs improvement. See my previous question here:

To summarize: We need to maintain low current distortion @ 400Hz, and when the input voltage is distorted according to my below screenshots.

Here is what has helped so far:

1. Reduce value of X-caps in EMI filter -- reduces the "transient response" effect (in the current waveform) at the "knee" of the clipped voltagewaveform. 

2. Increase ICOMP bandwidth, using lower value of. Here C(ICOMP) = 680pF ==> fc = ~15KHz according to the calculator

Here is what has not helped very much:

1. Changing switching frequency (tried +/- 20%, not much effect.)

2. Increase boost inductance to reduce DCM time (1200uH -> 1800uH -> 2500uH), 

3. Change VCOMP network

The distortion is still too much.

If you refer to these papers "On the Zero-Crossing Distortion in Single-Phase PFC Converter", Jian Sun, 2004 and "Demystifying Zero-Crossing Distortion in Single-phase PFC Converters", Jian Sun 2002, he shows that high current loop bandwidth alone cannot solve the zero-crossing distortion issue, but also requires the control loop to also be properly damped. I think he means, the phase margin of the control loop must be enough to prevent the control loop from oscillating as it transitions between DCM/non-conducting and CCM regions The 2002 paper clearly explains that a typical boost PFC stage has a leading current phase response, which worsens with higher line frequency. The issue is related to reverse biasing of the diode bridge which prevents the phase shifted PFC input current from pulling current continually throughout the cycle.

Many solutions have been suggested in various papers including:

1. Voltage (Vac) phase delay

2. Current reference (Iac) feed-forward 

But UCC28180 is a highly integrated PFC controller and certain internal blocks cannot be externally accessed. Vac is not sensed directly, so it does not appear possible to apply a phase delay. to Vac And, feedforward of Iac does not seem possible. Other controllers, such as ISL6730A, *seem* to better consider this type of issue. (Untested, but demo board waiting)

If we stay with UCC28180, we believe our best option is to increase the bandwidth of the control loop and to improve the phase margin of the loop. This should damp the overshoot and ringing of the current waveform near the zero crossing.

But the UCC28180 calculator only suggests a Type-I compensation network (single ICOMP capacitor). In my previous thread, I asked for starting values for a Type-II ICOMP network, but those values did not really seem correct in our testing, and only made the distortion worse. 

Its it possible for TI to modify the SLUC506 spreadsheet to include calculations for a Type-II compensator on ICOMP? Based on the information available in the datasheet, it is very difficult for us to do this ourselves. We also don't have enough experience to figure it out!

If you cannot modify the spreadsheet, can you help give us more clear equations on how to calculate the gain/phase response of the current loop with a Type-II network?

By the way, from SLUC506, what does a phase of -130° @ fc mean? I guess this is not the overall phase response of the current loop, just the current error amplifier?

Sorry for the long post. Thank you in advance,


  • Hello Tim, 

    Thanks for posting your question and sharing your detailed troubleshooting steps. We are reviewing this case and will get back to you within 48 hours.



  • Hi Tim,

    Thank you for the detailed description of the issue.

    It would be helpful if you can reshare the image showing distortion (before and after) as I cannot see it uploaded. It would help us debug and support the issue better.



  • Hi Harish,

    Thanks for your response. Which before and after would be helpful to see? (We've run so many tests.) 


    Below, I am copying a recent email I sent to a colleague on this issue...maybe it's of interest. I know it's very long:

    First you need to sell yourself on the idea that the PFC stage by itself draws a current which leads the voltage by some angle which depends on the line frequency. 


    This means that the PFC wants to draw a current ahead of the voltage, just by virtue of control loop theory – I’m waving my hands at this one. But the PFC is always (with the exception of a bridgeless PFC) precluded by a bridge rectifier. So, if the PFC wants to draw a current ahead of the voltage, this leads to a situation where the input voltage is still negative, but the PFC current wants to swing positive…but it can’t because the diode bridge is reverse biased (still conducting on the negative half of the voltage waveform.)



    So, then a dead zone appears where the PFC can simple not draw a current around the zero crossing. This is nothing to do with DCM, just diode bridge biasing and the inherent current-voltage phase relationship of a boost PFC stage. This dead zone is effectively unavoidable, and increases with increasing line frequency.

    When the voltage finally does swing positive the PFC will draw a high instantaneous current to get the current “back on track”. High di/dt – you can see this in the segment highlighted in yellow above. Various papers indicate that in order to limit the harmonic generation at this point, the PFC’s current control loop should be optimized to make this recovery without severe oscillation on the current waveform. Like any control loop, when the phase margin/stability margin is too low, (loop is underdamped), you get ringing on a step response. Current loop optimization is one aspect to improve this area.

    But if you take a look at the “raw” PFC current (i.e. when  all X-caps are removed, we can see that there is not really any severe oscillation around the zero-crossing. The current jumps up through the zero-crossing at high di/dt, as expected, but does not oscillate too much really.

    So then why do we get a current spike when the X-caps are put in? I think this the input filter’s transient response to the “step current” which occurs due to the above diode bridge/phase phenomenon. The PFC pulls a current through the EMI filter (of course). Increase the di/dt or dv/dt on any reactive circuit, and  you are bound to get some amount of ringing, unless it is properly damped. EMI filters are usually not resistively damped because that generally degrades the effectiveness of the filter, forcing you to use a bigger or more expensive filter overall.

    In this case, I found that if we add some resistive damping to the X-caps, then the ringing response may be subdued. See below.

    **In our testing, as of today 8/30, this did help subdue some ringing at the zero crossing, but the peak amplitude of the zero-crossing distortion was not really reduced, so our issue still persists.

    Next we will try to remove one or more of X-caps and see if that will reduce the "transient peak" near the zero crossing.


    Thanks a lot.


  • The above is not meant to confuse the original question - just some ideas about phenomenon we are seeing. It may be related to several things at the same time. 

    Still, we are interested in improving the current loop performance, as that gave us improvement in the past.


  • Hi Tim,

    Once again, thank you for the detailed inputs. 

    I was referring to your first post in this thread where you say that distortion is still too much and you have tried to attach a figure but that is missing. What I meant by before and after are your current image which is missing and the distortion image prior to making changes which helped improve current loop performance. 

    I have started going over this request and honestly there is a lot of useful information to go through. I will get back to you in a day or two.




    Thank you Harish. Appreciate the help.

    Please see the attached example before and after comparison. Here we reduced the X-filter capacitance by 1/3 and the harmonic distortion is generally improved, except the 13th harmonic still fails by about 3mA. (10mA limit). We think the high di/dt "recovery" of the PFC stage, after the voltage zero-crossing, drives high current through the EMI filter which results in a "transient response" of components in the EMI filter. It is also not so practical to continue to reduce the X-cap capacitance, due to EMI concerns, of course. 

    We will try some further experiments with UCC28180 ICOMP to see if we can reduce the "aggressiveness" of the control loop around the zero-crossing. Maybe we can improve the PFC's current response near the zero-crossing, smoother recovery of PFC current, less overshoot in EMI filter. Related to this idea, we ask for help on implementing a Type-II compensator on ICOMP. I think we will try something like this to see if it's helpful to improve the phase margin while maintaining good bandwidth. 

    Cip = 1nF

    Cic= 47nF + Ric = 4.7K

    ...using the following naming conventions:

    We also wonder if TI has knowledge of other successful customer solutions for 400Hz application, specifically meeting DO-160 over a wide power range. Perhaps a controller like UC3854B/UC2854B has better flexibility for "zero crossing compensation" and other similar ideas, since VRMS an IAC pins are available. On the other hand, UCC28180 does do quite a good job without much engineering effort! But I do see that UC3854B is advertised specifically for 400Hz use. Just wondering..

    Once again, I am sorry for so much detail - We've been working on this for a long time, trying to understand our possible paths for success. 

  • Hi Tim,

    Thank you for the detailed inputs.

    I think you are definitely on the right track to optimize the current loop with a type-2 compensator after getting some improvement with the reduced X-cap.

    Unfortunately we do not have such kind of reference design right now with UCC28180 for 400hz application. Attached sheet shows UCC28180EVM tested at 400Hz condition (using type-1 compensator), but it might not prove anything new to your case specifically. 

    2022.UCC28180EVM @115Vac 400Hz input.xlsx

    I will check on the applicability of a type -2 compensator to this system but the base equations are described in pages 9-11 of the following document.

    Current loop