UCD3020: UCD90320 HW schematic revew

This is an urgent please check asap

Hi

what kind of reboot cycle testing it is? could you provide more details?

What do you mean dead? does a reset(toggle the reset signal) bring the UCD90320 out of dead?

Schematics look fine.

Regards

Yihe

what kind of reboot cycle testing it is? could you provide more details?

Ans: the customer was running the reboot with PDU.

What do you mean dead? does a reset(toggle the reset signal) bring the UCD90320 out of dead?

Ans: We found I2C can not communicate it anymore, and RESET pin (G10) has 300 ohm resistance (before was 800 ohm)  from P3V3_DPM to GND. We believe there is an internal damage in the IC. 

Q1: Is there power ON / OFF and RESET timing requirement for UCD90320 IC?

Q2: Have TI or other customers experience this issue before? If yes, what is the root cause?

Q3: We will send the damaged IC for more detailed analysis.

Mike Hsu 

Hi

what's the frequency between reboot?  are stress tested done between reboot?

Are both UCD90320 dead? Did you probe the SYNC_CLK(K2) pin to see whether it has clock output? if it does have 5KHz clock, the device is alive. 

What's the voltage of V33A, V33D, BPCAP and RESET when the device is dead?

1. No

2. No

3. how many units are failed? what's the percentage?

Regards

Yihe

what's the frequency between reboot?  are stress tested done between reboot?

Ans: PDU was first turned ON and running stress test for 30 minutes, and then turned PDU off for 5 seconds, and turned ON again (AC power cycle)

Are both UCD90320 dead? Did you probe the SYNC_CLK(K2) pin to see whether it has clock output? if it does have 5KHz clock, the device is alive. 

Ans: One UCD90320 per PCB. The defected board has sent to Taiwan, we will measure it when we received board. 

What's the voltage of V33A, V33D, BPCAP and RESET when the device is dead?

Ans: The defected board has sent to Taiwan, we will measure it when we received board. 

How many units are failed? what's the percentage?

Ans: There is only one failed out of 3 boards.

My another question is what if GPIO pin pull up voltage is ealier than V33D, what is the risk? what is the initial state of these GPIO?

Thanks

Mike Hsu

Hi

it is up the current since if the GPIO is power up the internal esd diode maybe active

the best is to measure the failed unit 

regards

yihe

Hi Yihe

According to TI document SLVUB50C, when the IC is in RESET# or INITIAL state, its GPIO pins are in Hi-Z. So I don't think current or voltage can damage the GPIO pins.

Thanks

Mike 

Hi

It is different, under RESET or INITIAL UCD90320 is already power up.

but what you said in the early post is that GPIO is pull-up early than V33D. it means that the GPIO has voltage before UCD is power up.

Regards

Yihe

Hi Yihe

After the measurement, we would like to send the failed IC for further inspection.

Whom and what address I shall send to?

Hi

Please contact your local TI support team for the FA request.

Could you share the measurement of the requested data here?

Regards

Yihe

Hi there

Following is the resistance between signal pin to GND and siganl to V33D power.

As you see reset# pin of normal board is 13.2M ohm to GND, but the fail board became 281 ohm to GND.

V33D power pins to GND resistance is relatively smaller than normal board. ( 185 ohm VS 812 ohm)

HI

Have you powered up the returned unit to check the voltage(V33, Reset, BPCAP)?

Regards

Yihe

Hi

No, because we do not want to do futhur damage.

It's very clearly that something  not right.

HI

Sure, Understand the concerns.

We will process once the part is received. Please ship a control unit as well.

Regards

Yihe

Sorry 

We can only provide failed UCD90320 due to NDA 

How quickly TI takes to anaysis this IC?

This is a very urgent issue

Thanks

Mike Hsu

Hi Yihe

We found another fail piece after AC ON/OFF stress test yestarday. 

1. Can you check A1 & A2 schematic again that I attached in this session. I found unused GPIO pin should connect to GND according to https://www.ti.com/lit/ug/slvub50c/slvub50c.pdf

2. Is there power up / down timting between RESET_N pin and V33D power rail?

3. An AMONx pin is connected to ATX 12V with voltage divder circuit. This AMONx pin get  ATX 12V before V33D and RESET_N pin change to high. Will this AMON pin get damaged? 

PS. UCD90320 does not enable ATX 12V

Thanks

Mike Hsu

1. P3V3 =  P3V3_DPM is the same power rail. Both them are connected together.

2.  AMON2 (E1) is connected to ATX 12V.

3. Yes, it was tested under room temperature. X-ray looks fine and flying probe was tested as well. No issue was found.  

4.  Is there power up / down timting requirement between RESET_N pin and V33D power rail?

Hi

Your reset design is good. where is the RST_L from?

Regards

Yihe

Hi

RST_L does not connected to outside, it only connects to UCD90320 RESET_N (G10) pin.

Therefore, RESET_N became de-assert after P3V3_DPM power up.

Hi

I do not see any problem on the reset. Maybe there are something on the layout?

Regards

Yihe

I applied for CPR (Product return: CPR221071120)

Quality Tracking Number: QEM-CCR-2210-00001

This issue is point to EIPD (Electrically Induced Physical Damage) according to TI's response. However my question is can TI provide more information on absolution maximum rating for negative input voltage? For example. tolerance on negative voltage, time before damage.

What is TI suggestion to reduce negative voltage?

We have found abnormal waveform with some PSU that the negative voltage > -0.3V during power on.

Thanks

Mike Hsu