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Original question:

TPS3705: WDO pull high mechanism

TPS3705: Pulse width value specified by Texas instrument

Jean-Marc Brun-Rosoli
Prodigy 10 points

Part Number: TPS3705

Hello,

If I understand well, /WDO doesn't stay low when there is no signal on WDI. So the timing diagram for /WDO on the figure 7.1 is false.

The following sentence : " This event also reinitializes the watchdog timer" seems to justify why the pulse on /WDO is short, too short, less than 50 ns !

Why is the pulse width not specified in the datasheet ? What is its specified value ?

Thanks

  • 0
    TI__Mastermind 31580 points

    Hi Jean-Marc,

    The watchdog function is disabled if the WDI pin is left floating. If the WDI pin is driven but does not transition before the timeout period, then /WDO will assert low and signify a watchdog fault.

    If the watchdog is disabled, then detects a transition, the watchdog function will enable and start supervising.

    Are you asking about how long /WDO will assert low for?

    Also, please consider using the TPS3851, a newer and better-performing version of this device, instead.

    Thanks,

    Patrick

  • 0 in reply to Patrick Shalton
    Prodigy 10 points

    Hi Patrick,

    /WDO is used to reset the /MR of the TPS3705 and the /CLR of a flip-flop.

    I measure a pulse width for /WDO of 40ns. I think this value is short for the flip-flop input and I would like increase it  to 100ns for example.

    To do this, I delay a little bit the /WDO signal, which resets the /MR of the TPS3705. By reading the datasheet, I didn't understand that the /MR resets the /WDO signal.

    Thanks for the advice, I 'm looking at the TPS3851.

    Jean-Marc 

  • 0 in reply to Jean-Marc Brun-Rosoli
    TI__Mastermind 31580 points

    Hi Jean-Marc,

    Thanks for your context.

    On both the TPS3705 and TPS3851, /WDO will only assert low when /RESET is high; if /RESET is low, /WDO will default to a high-impedance state. However, the /WDO and /RESET outputs of the TPS3851 are open-drain, so you can tie them together with a pull-up resistor to create a unified output that asserts low upon either an undervoltage or watchdog fault, and remains low for 200ms.

    Please update this thread if you have any more questions about these devices or your design.

    Thanks,

    Patrick