UCC2808-1: two questions about how to use

Hi,

The duty is adjusted by COMP voltage - you can use any approach to adjust COMP voltage. Typically, in a closed-loop and DC-DC isolated converter, COMP is adjusted by sensing converter output voltage and through TL431 and opto-coupler, and an example is shown in the data sheet on several pages such as on page 1 and on the page of Typical applications. 50% duty is the maximum duty OUTA or OUTB can make. 47% is something before reach 50% when the feedback loop possibly to adjust to regulate the converter output voltage.

COMP can be pulled down to GND forever and no problem on the IC when it is powered on.    

Hi,

On Q2, when short COMP to FB, COMP only can get 2V typical. So the PWM comparator threshold would be 0.91V. CS to COMP has a typical offset 0.8V. So CS saw tooth in each Clock should be from 0 to 0.11V with 47us. 

But CS to COMP offset can be as high as 1.2V. If a device has such a parameter value, you won't get 47us. So to cover such a case, FB needs back to your circuit and design COMP voltage to make the PWM comparator threshold 1.2V, COMP = 2.64V, since FB = 2V, then you can calculate R2, R3 and R4. For this particular device, CS saw tooth would be from 0 to 0.4V in 47us, in order to get your specified waveform.

But after you do this, and when you have another device which has CS to COMP offset lower than 1.2V, then the CS saw tooth would need longer time to reach 1.2V PWM threshold. Then this device won't produce your waveform accurately.

So back to Questions, this device can produce the expected waveforms but you would need to tune up each device as due to the parameter variations, you cannot use one set design values to cover from device to device.

Hi,

There is another approach that can provide a bit better solution.

You would need to add a comparator and set up 6.1V as threshold. So when RC reaches > 6.1V (assume VDD = 13V), the comparator output change to > 0.5V, which will trigger Peak current comparator to turn off OUTA or OUTB. So this way can make 47us on and 3us off in theory. But again, CS peak comparator threshold is with min 0.45V and max 0.55V. So you may not get accurate 47us and 3us. But this approach should have better accuracy than the previous ones.

Since the threshold can be as high as 0.55V, so the external comparator output needs > 0.55V, but < 0.7V which is a threshold to trigger over current threshold and will trigger soft start to interrupt the operation.

Hi,

On the voltage comparator, something like LM311 or LM211 or LM211-Q1 can be used depending on your application temperature range. If you use a different part, please pay attention to the speed. LM311 has speed < 0.2us so it is ok in your applications. So please use speed < 0.2us parts.

Yes, the comparator output has to be within 0.55V and 0.7V to trigger max peak current threshold and not to trigger the over current limit. You can use a resistor divider if this range can be achieved.

Yes, your CS waveform is correct.

If you want to disable the IC, the datasheet suggestion is to pull down COMP pin. 

Hi,

Q1.

The pull-up needs to apply to every IC. In your circuit the very left will start a new cycle earlier or later than the other three depending on the very left one VDD/2 tolerance.

Q2.

I suggest you make an external sync circuit, or use the very left one to produce the sync, so the remaining 3 are ok to sync'ed.

Q3.

If your CS reset each cycle after sync, then the duty is from the sync till CS reaches above 0.5V. In this sense, the duty is not adjusted if the CS has a same slope. If you change the CS slope faster, the duty will be smaller, then your off time will be longer if you keep the sync clock same frequency. 

Hi,

CS should be with a saw tooth and peak at 0.55 to 0.65V. Your circuit cannot achieve this.