LP876242-Q1: Enable SPI CRC function

Hi Samuli

Customer tried enabling SPI CRC by I2C trigger but it didn't work.

Customer write 0x85=0x4(enable I2C CRC function) and comm_crc_err_mask is unmasked in the NVM setting setting, then customer on purpose send a write operation with wrong CRC value, but pmic didn't trigger the comm_crc_err_int bit. 

Would you help share your comments and solution?

Thanks 

HI Samuli

Customer feedback the four regulators were enable and the output voltage can be measured.

What's your comments? and would you help verified the SPI CRC function enabling via setting trigger_I2C_2 bit  (0x85=0x04)? 

Thanks 

Hi Ted,

TRIGGER_I2C_2 write should be correct, address 0x85 and data 0x4. Is the customer getting COMM_FRM_ERR_INT when writing with CRC enabled? Has the customer probed the SPI lines to see if the PMIC actually responds with 4 bytes for read command?

BR,

Samuli

HI Samuli

Thanks for your repliees.

Yes, after enabled SPI CRC function via SPI write 0x85=0x4 and unmasked the comm_crc_err(0x57), customer send the wrong CRC values write and expected to reaback the comm_crc_err_int in register 0x6A[1]. Customer didn't probed the SPI line with scope. 

Any comments? will ask customer to probe the SPI lines to see if the PMIC actually responds with 4 bytes for read command and let you know. 

Thanks 

Hi Samuli

Customer captured the waveforms via logic analyzer.   You can find the SPI behaviors in below screenshot.

And  you can find the interrupt register 0x6A readback via logic analyzer.

what's your comments ?

Thanks 

Hi Ted,

COMM_FRM_ERR_INT looks to be set on scope shots. Can they clear that and try again to see if COMM_CRC_ERR_INT appears then?

Also after writing TRIGGER_I2C_2 could they read address 0x11a to check what is register value? It is expected to be 0x07.

BR, Jari