TPS59650: Schematic Design Review

Hello Raj,

1. Tie the unused phase CSP pins to V3R3, float unused CSN & PWM pins. Note that you must use the lowest-number phase on a given rail (disabling phase 1 will also disable phases 2 & 3, disabling phase 2 will also disable phase 3).

2. I'd still recommend having a bulk capacitor, though it may not be necessary. You'd have to test that yourself. You could put a DNP cap on your test board and see if how the performance compares with and without the cap.

3A. The I_TDC_total is the maximum RMS current the rail is expected to drive.

3B. For thermal compensation, you can use an external NTC resistor in the compensation network. The B value will be specified in the thermistor's datasheet.

3C. This might be something used internally by the calculator. If you change the OSR setting, the calculated COCP-R pinstrap resistors change.

3D. I don't understand this question.

Also, does your application require IMVP7? There's a lot more options that can fit in a smaller space if not required.

Thanks,

Travis

Hello Travis,

Thank you so much the guide!

1) I am using First phase of CPU for CORE_VCC supply and First phase of GPU for UNCORE_VNN_S3 supply. Is this configuration correct?

2) Is it required to use DCR Sensing circuit for thermal compensation of 10A & 4A output current @ 1.0V?. If I can avoid using it then What would be the connections of CCSP & GCSP of first phase?.

Please let me know if you any other remarks my shared schematic. 

Thank You

Raj Kumar

Hello Raj,

1. That's the correct configuration.

2. If you wanted to avoid temperature compensation, you'd connect CCSN & CCSP to a voltage divider across the inductor. In this example, you'd remove RT1 & change the value of R4. However, that will effect the current sense accuracy.

Also, can you confirm if your application requires IMVP-7?

Thanks,

Travis

Hello Travis,

Greetings of the day!

Yes, My application requires IMVP-7 to support SVID interface. 

I have one more doubt regarding VR_ON pin the Package. 

As per datasheet, VR_ON comes under SVID interface with 1V I/O level. But I want to derive this pin externally (3.3V I/O level). Can I do so, as recommended Operating  conditions for VR_ON pin is given as 0V to 3.5V. 

Thank You

Raj Kumar

Hello Raj,

Driving the pin at 3.5V shouldn't be a problem.

Also, I should be able to complete the schematic review by the end of next week.

Thanks,

Travis

Hello Travis,

Thank you for confirming the VR_ON I/O Voltage.

Yes Please, I'll be waiting for your comments on schematic if any. 

Thank You 

Raj Kumar

Hi Raj,

Apologies for the inconvenience, but I need to delay the schematic review. I should have the review complete by the end of Tuesday.

Thanks,

Travis

Hi Travis, 

Thank you so much for the schematic review & comments. 

I wanted to clear one doubt from your comments on the schematic. 

you have commented "MINIMUM IMAX CURRENT IS 20A (133mV)". What do you mean by that? Because I have calculated the IMAX current value using the formula given in datasheet, and it comes 4A (CPU), 10A (GPU). 

Please elaborate your above comment. 

Kindly refer your commented schematic from previous message. 

Thank You

Raj Kumar

Hi Raj,

My concern is that the IMAX current cannot be set that low. I have contacted another internal person to confirm, and I'll get back to you by Wednesday (US time).

Thanks,

Travis