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TPS548A28: Layout problem for analog peripheral passives

Part Number: TPS548A28
Other Parts Discussed in Thread: TPS61089

Dear Experts / Professionals,

Related Fig-1 & 2. In our situation, Section-A and Section-B one of them must be placed on the opposite side of the TPS548A28. Which one should be placed on the opposite side of it to have less effect on the characteristics?

In the related situation of TPS61089 (URL below), it is pointed out that placing the FB circuit on the opposite side of the chip has less effect on the characteristics. Can we take the same point of view for the TPS548A28?

About the optional circuit of CFF. What is the purpose of this component?(How does it work in what situations?) And how do we choose a capacitor value in a particular situation?




Related situation:

Thank you,

  • I would place the B components on back side.   

    The mode  (Rmode) is latched in before startup and will not be sensitive afterward when the device is operating. 

    SS/REFIN capacitor sets the soft start time.   Connect the SS/REFIN capacitor with via near VSNS- pin.   

    RTRIP sets the current limit threshold and used during operation.  Make sure the RTRIP resistor ground connection is a quiet ground. 

    The Cff is the feedforward capacitor.   The Cff gives a phase boost in the control loop.       

    At the crossover frequency the phase margin should be greater than 45 degrees.   

    The Cff is often used to increase the crossover frequency to improve transient response.

    On the product folder, there is an excel sheet that can used to estimate the Cff value. 

  • Thank you for sharing your point of view. Based on your advice, we will reflect it in the design.

  • Please let me confirm one thing. Is it correct to understand that it is desirable to place the FB circuit on the same side as the device because the FB takes the voltage like a differential through Vsns(+/-) (i.e. very sensitive circuit)

  • The FB/VSNS- pins are high impedance and can be sensitive and it is preferred the components should be close to the device.

    When placing components on same layer  as device, the sense lines need to stay away from inductor, sw nodes and high frequency clock signals.   

    If using a via the same advice applies, but now all layers need to be reviewed for high frequency clock signals near the vias. 

    When using vias connecting the feedback components to FB and VSNS-  you are placing vias on the most sensitive pins and at risk of noisy traces on other layers coupling to these pins. 

  • Thank you for your advice. We will be pay attention to the FB via-s and trace connections to avoid noisy structures.