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TPS40210: Low Current Discontinuous Design

Andrew Greensted
Prodigy 250 points
Other Parts Discussed in Thread: TPS40210

Hi All,

I'm designing a boost circuit based on the TPS40210 with the following specification:

VIN 15V
VOUT 150V
VD 0.9V
FSW 320kHz
L 100uH
IOUT 15mA

The output current can vary from 0 to 15mA, so I've chosen to use discontinuous conduction mode. I have some questions regarding the required compensation network and the inductor current requirements, but first I'd like to give my calculations to see if they look sensible. (Equation numbers used below are those from the TPS40210 datasheet).

Here is the spreadsheet I used to make the calculations: 0513.TPS40210 DCM.xlsx

  • The duty cycle is 0.64 (using equation 3)
  • The critical output current is 22.38mA (equation 4) as this is greater than the required 15mA, control should stay in discontinuous mode.
  • I've selected CT = 100pF and RT = 510K, this gives the 320kHz switching frequency.
  • Based on Eqn 6, the sense resistor is 325mR, I've selected 330mR which gives a trip current of 25mA
  • On time is about 2us (Eqn 11), which gives CIFLT = 100pF, RIFLT = 2K (Eqn 12)
  • Using Eqn 57, RFB = 100K RBIAS = 470R

Inductor Currents

I'd like to calculate the inductor peak current. When in discontinuous mode are equations 34 & 39, still usable? From a different application note (SLVA061, Page 8) the peak inductor current is given as (VI x D) / (L x FSW), is this OK to use?

Compensation Network

I'm struggling quite a lot to get a complete grasp of calculating the required compensation network component values. If I understand correctly the situation is more relaxed in discontinuous mode. Are equations 22 to 29 still appropriate?

Switching Frequency

Are there any advantages in using a higher switching frequency? The equations suggest that a higher FSW forces the use of a lower inductance to maintain discontinuous mode. The load is actually a fast switching circuit (around 100kHz) that requires bursts of current every time it switches. Would a faster switching frequency improve the controllers ability to maintain the correct output voltage?

This is a lot of info and questions, so many thanks for your patience.
Thanks
Andy

  • 0
    TI__Genius 17240 points

    Hi Andy,

    1. Duty cycle: I think the equation (3) is not correct. It should be D = sqrt(2*(VOUT+VD-VIN)*IOUT*L*fsw/(VIN)^2), which gives 0.76 with your specifications.

    2. Inductor currents: Equation 34 and 39 are for CCM. (VIN*D)/(L*fsw) will work.

    3. Compenstion network: Equation 22-29 is actually based on the assumption of DCM operation, where Rout is the maximum output impedance (Equation (58)). So you can follow the steps in the design example. You can also refer to the following article for understanding the small-signal model of DCM boost converter with peak-current-mode control.

    http://focus.ti.com/download/trng/docs/seminar/Topic_3_Lynch.pdf 

    4. Switching frequency: higher Fsw will allow the controller to have a higher crossover frequency. In other words, the controller can react faster. With the same amount of output capacitance, the output voltage will have less deviations due to load transient. Or for the same output voltage deviation requirement, the output capacitance can be reduced to save footprint on the board and the cost. The lower inductance will also help the transient response because less inertia of the current, in other words, the inductor current can increase/decrease faster. But smaller inductance, large ripple, more loss. The higher end of Fsw will be limited by the efficiency since the higher Fsw, the more swiching loss.

    Regards,

    Na

  • 0 in reply to Na Kong
    Prodigy 250 points

    Hi Na,

    Many thanks for your response. I did wonder about the DCM Duty cycle equation, it didn't seem to compare with any other I'd found in alternate datasheets. Thanks for the link, this has been a great help.

    I've added the compensation network calculations to my spreadsheet. The problem is what to use for Rout. The output current requirements range from almost 0 to 15mA. Taking the current required by the feedback network as the minimum (about 1.5mA), this leads to a maximum Rout of (150/1.5) 100kohm. After calculating the network component values, they seem to be very unrealistic (large resistor and very small capacitor values).

    It seems I need to reduce the sense resistor value considerably to achieve more sensible compensation network component values. However, I'm concerned that with the small currents I'm using this will generate a very small sense resistor voltage. Is this going to be a problem?

    Would you mind taking another look at my spreadsheet and checking the results look sensible?

    3443.TPS40210.xls

    Thanks again

    Andy

  • 0 in reply to Andrew Greensted
    Prodigy 250 points

    Below are a schematic and waveform plot for the circuit I have so far. The controller is staying in DCM through the whole output current range. However, the switching node waveform in yellow (junction of L1, U2 and D1) shows a second pulse. Do you know the cause of this? The FET gate drive is shown in the top trace (blue).

    Thanks

    Andy

     

  • 0 in reply to Andrew Greensted
    TI__Genius 17240 points

    Hi Andy,

    The second pulse on switching node is caused by the oscillation between the inductor and the parasitic capacitance at the switching node after inductor current depletes. It will induce switching loss when the FET is turned on. If you are fine with the efficiency, you don't need to worry about that. Same as the compensation design. The step-by-step design procedure given by the datasheet is just a guideline. If the converter already works for the whole load range and load transient response is acceptable, you don't have to follow the numbers given by the datasheet.

    Regards,

    Na

  • 0 in reply to Na Kong
    Prodigy 250 points

    Hi Na,

    Thanks again for the feedback. Although efficiency isn't a deal breaker, it is always nice to improve it! Out of interest what could be done to reduce the oscillation? You said its due to parasitic capacitance, do you think PCB layout or component parasitics are the more likely culprit? Are there any datasheets/app notes that deal with this.

    Thanks

    Andy

  • 0 in reply to Andrew Greensted
    TI__Genius 17240 points

    Hi Andy,

    The parasitic capacitance is mainly the output capacitance of the MOSFET and junction capacitance of the diode.  What I can think of to reduce the oscillation is using snubber circuit. Simple RC snubber may help reduce the peak of the ringing but itself will dissipate some energy. If you are interested, the following is a very good reference on snubber circuit. Non-dissipative snubber may help the efficiency at the expense of circuit complexity and design effort.

    http://focus.ti.com/lit/an/slup100/slup100.pdf

    Regards,

    Na