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Original question:

TPS65988: TPS65988 IRQ question

TPS65988: Clarification on interrupt registers and signal(s) wanted

Tobias Johansson
Prodigy 50 points
Part Number: TPS65988

Hello!

I would like some insight in the interrupt registers and signal(s) on the TPS65988.

First of all, according to the answer @ https://e2e.ti.com/support/interface-group/interface/f/interface-forum/777183/tps65988-tps65988-irq-question

- to get the interrupts currently active from, say Port 1 (address 0x20 lets say), I read register 0x14 (IntEvent1) from address 0x20, and I do not have to "care about IntEvent2"?

What I am actually wondering is the distinction between IntEvent1, IntMask1, IntClear1, IntEvent2, IntMask2 and IntClear2 - what does the 1 and 2 mean and how do they interact with the I2C2_IRQ signal (pin 34)?


(From Technical Reference Manual)

The reason I have this question is that:

When an interrupt occurs (lets say PlugInsertOrRemoval) on Port 2, the I2C2_IRQ signal (pin 34) goes low/active - as it should, and I can read the IntEvent2 register and see that the PlugInserOrRemoval interrupt is active, handle it and then write the corresponding bit to IntClear2 to clear it (and the I2C2_IRQ signal goes high/inactive).

However, when replicating the same thing on Port 1, the I2C2_IRQ signal never "goes low", but when reading the IntEvent1 register I can see the expected interrupt being active, and writing the corresponding bit high to IntClear1 clears it from IntEvent1.

(Same mask is written to both IntMask1 on 0x20 and IntMask2 on 0x24.)

Thanks for any help in resolving issue.

  • 0
    TI__Mastermind 34506 points

    Hi Tobias,

    Looking into and will provide response by end of the week. 

    Thanks and Regards,

    Raymond Lin

  • 0
    TI__Genius 15275 points

    Hi Tobias,

    This answer is similar to the E2E post you attached. Each port is given its own I2C slave address based on the ADCIN2 strapping. Each port will also then have individual configurations based on SPI_POCI and ADCIN1. 

    Therefore, you are correct if Port 1 slave address is 0x20, you will only need to read register 0x14 for IntEvent1 to see the interupt event for Port 1. The 1 and 2 are identifiers for the distinction between port 1 and port 2. IntEvent1, IntMask1, IntClear1 all correlate to Port 1 and IntEvent2, IntMask2 and IntClear2 all correlate to Port 2. These interact with I2Cx_IRQ since IntEvent1 is the interupt event bit field for it. 

    "However, when replicating the same thing on Port 1, the I2C2_IRQ signal never "goes low", but when reading the IntEvent1 register I can see the expected interrupt being active, and writing the corresponding bit high to IntClear1 clears it from IntEvent1." - If you are replicating this for Port 1, then this will not be reflected on I2C2_IRQ, instead it will be reflected on I2C1_IRQ.

    Very Respectfully,

    Brandon Beader