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Original question:

TPS65988: SPI Flash Firmware update over i2c process FLem 4CC

TPS65988: How to setup power delivery limit to 27W?

Sofian Teja
Prodigy 80 points
Part Number: TPS65988
Other Parts Discussed in Thread: TPS65987D

Hi TI Experts,

I would like to confirm if this below steps is the correct way to calculating the watts from USB-PD register.

We want to configs the USB_PD to have the limit for delivery power to 27W. (3A @ 9V)

I checked the TPS65988 Specs, there are port configuration (0x28) and port control (0x29). 

Would you please take a look this below, if those bits are correct,  that we can config to limit the power to 27W ?

For current register I calculated is 48W. 

I calculated from these 2 registers 0x28 and 0x29.

1. PORT_CONFIGURATION.VBUS_UVP_OVP_SS_VBUS_OVPTRIPPOINT  0x26 -->  0x26 * 0.32V + 3.84V = 16V.

2.  PORT_CONTROL.TYPECCURRENT 0x2  --> 3.0A * 16V = 48 W.

USB_PD:38 [PORT{0-1}]
Id TPS6598X_REG[0] Offset Width Value
-------------------------------------------------------
[24] PORT_CONFIGURATION 0x0028 8 0x0000000033363109
-------------------------------------------------------
< 1> PORT_CONFIGURATION.PORT_CONFIGURATION_TYPECSTATEMACHINE 0:1 0x0000000000000001
< 2> PORT_CONFIGURATION.PORT_CONFIGURATION_RECEPTACLETYPE 3:5 0x0000000000000001
< 3> PORT_CONFIGURATION.PORT_CONFIGURATION_AUDIOACCESSORYSUPPORT 6:6 0x0000000000000000
< 4> PORT_CONFIGURATION.PORT_CONFIGURATION_DEBUGACCESSORYSUPPORT 7:7 0x0000000000000000
< 5> PORT_CONFIGURATION.PORT_CONFIGURATION_SUPPORTTYPECOPTIONS 8:9 0x0000000000000001
< 6> PORT_CONFIGURATION.PORT_CONFIGURATION_VCONNSUPPORTED 11:12 0x0000000000000002
< 7> PORT_CONFIGURATION.PORT_CONFIGURATION_USB3RATE 13:14 0x0000000000000001
< 8> PORT_CONFIGURATION.VBUS_UVP_OVP_SS_VBUS_SETUVPTO4P5V 16:16 0x0000000000000000
< 9> PORT_CONFIGURATION.VBUS_UVP_OVP_SS_VBUS_UVPTRIPPOINT5V 17:19 0x0000000000000003
<10> PORT_CONFIGURATION.VBUS_UVP_OVP_SS_VBUS_UVPTRIPHV 20:22 0x0000000000000003
<11> PORT_CONFIGURATION.VBUS_UVP_OVP_SS_VBUS_OVPTRIPPOINT 23:28 0x0000000000000026
<12> PORT_CONFIGURATION.VBUS_UVP_OVP_SS_VBUS_OVPUSAGE 29:30 0x0000000000000001
<13> PORT_CONFIGURATION.VBUS_UVP_OVP_SS_VBUS_HIGHVOLTAGEWAR_NINGLEVEL 31:31 0x0000000000000000
<14> PORT_CONFIGURATION.VBUS_UVP_OVP_SS_VBUS_LOWVOLTAGEWARN_INGLEVEL 32:32 0x0000000000000000
<15> PORT_CONFIGURATION.VBUS_UVP_OVP_SS_SOFTSTART 33:34 0x0000000000000000
<16> PORT_CONFIGURATION.VBUS_UVP_OVP_SS_ENABLEUVPDEBOUNCE 36:36 0x0000000000000000
<17> PORT_CONFIGURATION.VOLTAGETHRESASSINKCON_TRACT 40:47 0x0000000000000000
<18> PORT_CONFIGURATION.POWERTHRESASSOURCECO_NTRACT 48:55 0x0000000000000000
-----------------------------------------------------------------------------------------------

USB_PD:38 [PORT{0-1}]
Id TPS6598X_REG[0] Offset Width Value
--------------------------------------------
[25] PORT_CONTROL 0x0029 4 0x0009c0c2
--------------------------------------------
< 1> PORT_CONTROL.TYPECCURRENT 0:1 0x00000002
< 2> PORT_CONTROL.DISABLEPD 2:3 0x00000000
< 3> PORT_CONTROL.PROCESSSWAPTOSINK 4:4 0x00000000
< 4> PORT_CONTROL.INITIATESWAPTOSINK 5:5 0x00000000
< 5> PORT_CONTROL.PROCESSSWAPTOSOURC_E 6:6 0x00000001
< 6> PORT_CONTROL.INITIATESWAPTOSOURCE 7:7 0x00000001
< 7> PORT_CONTROL.PROCESSVCONNSWAP 10:10 0x00000000
< 8> PORT_CONTROL.PROCESSSWAPTOUFP 12:12 0x00000000
< 9> PORT_CONTROL.INITIATESWAPTOUFP 13:13 0x00000000
<10> PORT_CONTROL.PROCESSSWAPTODFP 14:14 0x00000001
<11> PORT_CONTROL.INITIATESWAPTODFP 15:15 0x00000001
<12> PORT_CONTROL.AUTOMATICIDREQUEST 16:16 0x00000001
<13> PORT_CONTROL.FORCEUSB3GEN1 18:18 0x00000000
<14> PORT_CONTROL.EXTERNALLYPOWERED 19:19 0x00000001
<15> PORT_CONTROL.AUTOMATICSINKCAPREQ_UEST 20:20 0x00000000
<16> PORT_CONTROL.SINKCONTROLBIT 21:21 0x00000000
<17> PORT_CONTROL.RESISTOR15KPRESENT 24:24 0x00000000
<18> PORT_CONTROL.DCDENABLE 25:25 0x00000000
<19> PORT_CONTROL.CHARGERADVERTISEENABL_E 26:28 0x00000000
<20> PORT_CONTROL.USBDISABLE 29:29 0x00000000
<21> PORT_CONTROL.CHARGERDETECTENABLE 30:31 0x00000000
------------------------------------------------------------

Thanks,
Sofian

  • 0
    TI__Mastermind 37855 points

    Hi Sofian,

    Sofian Teja said:
    2.  PORT_CONTROL.TYPECCURRENT 0x2  --> 3.0A * 16V = 48 W.

    TypeC Current is for Non-PD Type C Source connections(Generic 5V/3A). It does not limit in the case of USB-PD. The USB-PD current limit is calculated form the negotiated PDO's Max Current * Peak Current.

    Sofian Teja said:
    We want to configs the USB_PD to have the limit for delivery power to 27W. (3A @ 9V)

    If you want to limit a PD controller to to 9V/3A max, you can limit the Source/Sink PDOs offered.

    Within the Transmit source capabilities register, you can limit the number of PDOs and the max power offered.

    Within the PDO, you can set the voltage, the max current, and the peak current, effectively limiting the power. If you do not want the PD to offer/negotiate PDOs, with higher power, you can remove them by decreasing the "Number of Bank 0 Source PDOs".

    It seems like you are trying to program the registers over I2C. I would recommend getting familiar with the general PD operations using the APP Config GUI and an EVM. Within the GUI, you can enable "Show Bitfield Ranges", which will display bit locations for the values. This may make it easier to (1) prototype certain configurations and (2) know which registers and bits need to change.

    Thanks and Regards,

    Chris

  • 0 in reply to Christopher Lim1
    Prodigy 80 points

    Hi Chris,

    We met a problem while trying to install the TI APP config GUI. so we still trying.

    another question is while in this below I read the register 0x32 the TX Source Capabilities.

    USB_PD:38 [PORT{0-1}]
    Id TPS6598X_REG[0] Offset Width Value
    -------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    [31] TX_SOURCE_CAPABILITIES 0x0032 64 02fc0000000000002c9101052cd1828b2cc103002cb1040045410600000000000000000001900101000000000000000000000000000000000000000000000000
    -------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    < 1> TX_SOURCE_CAPABILITIES.HEADER_BANK_TXSOURCEBANK0NUMPDOS 0:2 0x02
    < 2> TX_SOURCE_CAPABILITIES.HEADER_BANK_TXSOURCEBANK1NUMPDOS 3:5 0x00
    < 3> TX_SOURCE_CAPABILITIES.PDOS_TO_ADVERTISE_BANK_0_ADVERTISEDPDOBANK0 10:15 0x3f
    < 4> TX_SOURCE_CAPABILITIES.PDO_BANK_SELECT_ACTIVEPDOBANK 16:16 0x00
    < 5> TX_SOURCE_CAPABILITIES.PDO_BANK_SELECT_ACTIVEPDOBANKFOLLOWSEXTERNALLYPOWERED 17:17 0x00
    < 6> TX_SOURCE_CAPABILITIES.SOURCE_SELECTION_BANK_0__PDO1SOURCEBANK0 32:33 0x00
    < 7> TX_SOURCE_CAPABILITIES.SOURCE_SELECTION_BANK_0__PDO2SOURCEBANK0 34:35 0x00
    < 8> TX_SOURCE_CAPABILITIES.SOURCE_SELECTION_BANK_0__PDO3SOURCEBANK0 36:37 0x00
    < 9> TX_SOURCE_CAPABILITIES.SOURCE_SELECTION_BANK_0__PDO4SOURCEBANK0 38:39 0x00
    <10> TX_SOURCE_CAPABILITIES.SOURCE_SELECTION_BANK_0__PDO5SOURCEBANK0 40:41 0x00
    <11> TX_SOURCE_CAPABILITIES.SOURCE_SELECTION_BANK_0__PDO6SOURCEBANK0 42:43 0x00
    <12> TX_SOURCE_CAPABILITIES.SOURCE_SELECTION_BANK_0__PDO7SOURCEBANK0 44:45 0x00
    <13> TX_SOURCE_CAPABILITIES.SOURCE_SELECTION_BANK_1__PDO1SOURCEBANK1 48:49 0x00
    <14> TX_SOURCE_CAPABILITIES.SOURCE_SELECTION_BANK_1__PDO2SOURCEBANK1 50:51 0x00
    <15> TX_SOURCE_CAPABILITIES.SOURCE_SELECTION_BANK_1__PDO3SOURCEBANK1 52:53 0x00
    <16> TX_SOURCE_CAPABILITIES.SOURCE_SELECTION_BANK_1__PDO4SOURCEBANK1 54:55 0x00
    <17> TX_SOURCE_CAPABILITIES.SOURCE_SELECTION_BANK_1__PDO5SOURCEBANK1 56:57 0x00
    <18> TX_SOURCE_CAPABILITIES.SOURCE_SELECTION_BANK_1__PDO6SOURCEBANK1 58:59 0x00
    <19> TX_SOURCE_CAPABILITIES.SOURCE_SELECTION_BANK_1__PDO7SOURCEBANK1 60:61 0x00
    <20> TX_SOURCE_CAPABILITIES.PDO_1_TXSOURCEPDO1BANK0 64:95 0x0501912c
    <21> TX_SOURCE_CAPABILITIES.PDO_2_TXSOURCEPDO2BANK0 96:127 0x8b82d12c
    <22> TX_SOURCE_CAPABILITIES.PDO_3_TXSOURCEPDO3BANK0 128:159 0x0003c12c
    <23> TX_SOURCE_CAPABILITIES.PDO_4_TXSOURCEPDO4BANK0 160:191 0x0004b12c
    <24> TX_SOURCE_CAPABILITIES.PDO_5_TXSOURCEPDO5BANK0 192:223 0x00064145
    <25> TX_SOURCE_CAPABILITIES.PDO_6_TXSOURCEPDO6BANK0 224:255 0x00000000
    <26> TX_SOURCE_CAPABILITIES.PDO_7_TXSOURCEPDO7BANK0 256:287 0x00000000
    <27> TX_SOURCE_CAPABILITIES.PDO_1_TXSOURCEPDO1BANK1 288:319 0x01019001
    <28> TX_SOURCE_CAPABILITIES.PDO_2_TXSOURCEPDO2BANK1 320:351 0x00000000
    <29> TX_SOURCE_CAPABILITIES.PDO_3_TXSOURCEPDO3BANK1 352:383 0x00000000
    <30> TX_SOURCE_CAPABILITIES.PDO_4_TXSOURCEPDO4BANK1 384:415 0x00000000
    <31> TX_SOURCE_CAPABILITIES.PDO_5_TXSOURCEPDO5BANK1 416:447 0x00000000
    <32> TX_SOURCE_CAPABILITIES.PDO_6_TXSOURCEPDO6BANK1 448:479 0x00000000
    <33> TX_SOURCE_CAPABILITIES._PDO_7_TXSOURCEPDO7BANK1 480:511 0x00000000
    -----------------------------------------------------------------------------------------------------

    I check the TRM 

    Regarding your statement below, can you give more details like how to config in register offset 0x32 ? from the above registers bits.

    " if you want to limit a PD controller to to 9V/3A max, you can limit the Source/Sink PDOs offered.

    Within the Transmit source capabilities register, you can limit the number of PDOs and the max power offered.

    Within the PDO, you can set the voltage, the max current, and the peak current, effectively limiting the power. If you do not want the PD to offer/negotiate PDOs, with higher power, you can remove them by decreasing the "Number of Bank 0 Source PDOs".   "

    Advertise mask = not advertise  => 0x0  is this the correct one ?

    < 3> TX_SOURCE_CAPABILITIES.PDOS_TO_ADVERTISE_BANK_0_ADVERTISEDPDOBANK0 10:15 0x3f   => 0x0 ? 

    Maximum current = 3A   ?  which bits related to max current ? 0x3

    Voltage= 9V    ?    which bits related to voltage ?    0x9

    Thanks,
    Sofian

  • 0 in reply to Sofian Teja
    TI__Mastermind 37855 points

    Hi Sofian,

    Sofian Teja said:
    We met a problem while trying to install the TI APP config GUI. so we still trying.

    Is this the gui found on the TPS65987D project page?

    https://www.ti.com/product/TPS65987D

    Sofian Teja said:
    Regarding your statement below, can you give more details like how to config in register offset 0x32 ? from the above registers bits.

    The easiest way would be to adjust the settings in the GUI and see the corresponding bits that change. The descriptions explain what the bits represent pretty well. Are there any specific ones that are confusing?

    Sofian Teja said:

    " if you want to limit a PD controller to to 9V/3A max, you can limit the Source/Sink PDOs offered.

    Within the Transmit source capabilities register, you can limit the number of PDOs and the max power offered.

    Within the PDO, you can set the voltage, the max current, and the peak current, effectively limiting the power. If you do not want the PD to offer/negotiate PDOs, with higher power, you can remove them by decreasing the "Number of Bank 0 Source PDOs".   "

    When setting the PDOs, (bytes 9-36 for bank 0), you will need to follow the Power Data Object(PDO) format for source objects as described in the USB-PD spec.

    Section 6.4.1.2 in the USB-PD spec goes much more into depth about Source PDOs and what each bit represents. For a fixed source PDO, the format can be seen in the table below.

    Thanks and Regards,

    Chris