BQ4050: There was no ACK response during the communication

Dear Shirish

Thanks for your reply ,but customer have below concern ,pls help to give a suggestion :

1. The logic of the DC board program is that when the BMS cannot be read, the relevant register data will not be read. Only the device address 0X16 is written, but the BMS has not responded.
This has not been answered, much like BQ4050 crash, our software set SCL SDA low at the same time, it recovered, we need to confirm with TI whether BQ4050 has such a reset mechanism.
TI says the frequency is too fast, we set the time to 5 seconds to read once, log data will be the same error.
2. At present, the communication problem has been modified to avoid the DC board software, extending the ACK waiting time (error still occurs after extension), and adding that when BMS crashes, the SCL SDA will be set to low for 1 second at the same time (no error will be reported after the low level is added), which is currently being tested and verified by the full function. -- This logic needs to be verified with TI to ensure reliability.

Hello Gabriel,

1. What speed is the SMBus communication in KHz?

2. What is the interval between register reads in seconds?

SDA and SCL must change per the SMBus specification. If both are pulled low simultaneously, the BQ4050 may get confused and treat is as a start or an invalid pulse. If there was already a start bit sent previously and there was no Stop bit, then it will just continue the transaction.

Dear Sirish

1. SMBus frequency is 80kHz

2, read the register interval time is 200ms, that is, 200ms read a register.

3. Why can low SDA and SCL solve the problem that BQ4050 does not respond?

4. If the start bit is sent, but the ACK of BQ4050 is not received, the timeout (> 14ms) When there is no ACK, our host will send a stop bit.

Hello Gabriel,

The frequency and interval are ok.

A low SCL will probably result in recovery because the BQ4050 will timeout the transaction.

I would recommend using an analog oscilloscope to check the communication waveforms for noise.

Dear Shirish

Below is SDL and SCK waveform ,could u hlep to check it ?

It looks ok and ends with a clock stretch. Does the slightly higher "low" represent the bq4050?

Dear Shirish

The slightly higher low level is the ACK signal of BQ4050.

May I ask if it is possible that the anti-interference ability of I2C is relatively poor leading to EV2400 can not read the data

Please clarify what you mean with "anti-interference ability"?

Dear Dominik

The "anti-interference ability"  means maybe other high frequecy noise . 

This BQ4050 board near the power inverter , and the application is protable power station . Below is customer's schemetic and PCB ,could u help to check and give some advice ?

This is second layer:

This is top layer

this is some part of the SMbus schemetic , MCU side have two 4.7K Ω pull up resistor .

I would first check, if disabling the interference source makes a difference in communication errors. If so, I'd check the signal quality on SMBC and SMBD. You could try using lower Ohm pull-ups, in case the total capacitance on the bus causes slow edges. And reduce the SMBC frequency.