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UCD3138: Sync FET Soft On/Off using Ramp Module

Part Number: UCD3138

I  find the example code of UCD3138HSFBEVM029 EVM firmware . Use Frontend 2 ramp module do SR soft on. Set the RAMPDACEND.RAMP_DAC_VALUE to 1100 according to EVM firmware. The pwm mode is normal . But i find that the SR duty can not above 70%. And the DPWMA duty is only 12%.  So i want to know that how to set the RAMPDACEND.RAMP_DAC_VALUE. What does this value relate to? Thanks!

  • Hello,

    1, Can you share a waveform which can show "SR duty can not above 70%. And the DPWMA duty is only 12%" you mentioned?

    2, what kind of control mode you selected? PCM or VCM?

    thanks 

  • Hi,Bliss:

    1. The waveform as follow: The switch frequency is 160KHz. 

                 

    2. the control mode is VCM. The PWM mode is normal. The duty come from filter.

    Thanks!

  • Thanks Liwei,

    May I ask you if you have configured the EV4 to 0? If you already have configured EV4 to 0, Could you share the EV1,EV2,EV3 and EV4 configuration of code?  If not, try zero for EV4. BTW, did you try to change the RAMPDACEND.RAMP_DAC_VALUE value?  Can you tell me all of the changes compare to demo code?

    thanks 

  • Hi,Bliss:

               The DPWM EV4 set period subtract deadtime.

                EV1 = 20 EV2 from fiter output EV3=period>>1

                I try to change the RAMPDACEND.RAMP_DAC_VALUE value and the issue is slove. but  I want to know how to set the value suitably. i afraid that the value set wrong that the DPWMA and DPWMB maybe open at the same time to case the module breakdown.

                If this value is set incorrectly, does the normal mode of DPWM guarantee the correct output waveform?

  • Liwei,

    follow the following two tips.

    1, configure the RAMPDACEND.RAMP_DAC_VALUE = PERIOD - DT (you need).

    2, EV4 configure to 0.

  • Hi,Bliss:

                1. if the RAMPDACEND.RAMP_DAC_VALUE set to PERIOD - DT, how to set the value of SYNC_FET_RAMP_START. 0?

                2. Now EVT4 confugure to PERIO - DT.

                I want to know which the register above(RAMPDACEND.RAMP_DAC_VALUE and EVT4 ) is high priority. It can guarantee the correct output waveform.

  • Liwei,

    1, configure a value of SYNC_FET_RAMP_STAR which is greater than EV1.

    2, Both EV4 and RAMPDACEND.RAMP_DAC_VALUE have to be considered.

    the falling edge of DPWMB is decided by the EV4 if EV4 < RAMPDACEND.RAMP_DAC_VALUE or RAMP is disabled.

    the falling edge of DPWMB is decided by the AMPDACEND.RAMP_DAC_VALUE if EV4 > RAMPDACEND.RAMP_DAC_VALUE.

    if you configure AMPDACEND.RAMP_DAC_VALUE = PERIOD - DT and EV4 = 0, that means EV4 > AMPDACEND.RAMP_DAC_VALUE -> falling edge of DPWMB is decided by the AMPDACEND.RAMP_DAC_VALUE.

    EV4 = 0 means EV4 is placed at the begin of next period and also means the end of current period.

    please refer to the RTM page 122 UCD31xx Technical Reference Manual (Rev. D) (ti.com)

    thanks 

  • Hi,Bliss:

                Thank you very much!