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TPS25750: full flash & low region binary

Part Number: TPS25750
Other Parts Discussed in Thread: TPS65982,
  1. What is the different between low region & full flash binary? Is there any documentation describing it?
  2. In MCU-based nonintegrated USB PD battery-charger implementation, which patch bundle binary/c array file to be used? low region or full flash in this MCU-based configuration?
  3. How PBMs command is used to differentiate full flash or low region binary?
  4. After PBMs is issued, what is the command to transfer the patch bundle data?
  5. Is there any example project using TI MCU to download the patch bundle to the PD?

Thanks.

  • Good Afternoon Ck,

    I will review your question and provide you an answer by 5/23, EOB.

    Kind regards,

    Conner Gillette

  • 1. There is no difference, the low region and high region are identical.

    Documentation from the TPS65982 for general overview of flash binary (Figure 1 is most helpful): https://www.ti.com/lit/an/slva783a/slva783a.pdf

    Technical Reference Manual for TPS25750 showing patch loading process specific to TPS25750 (Figure 4-1): https://www.ti.com/lit/ug/slvuc05a/slvuc05a.pdf

    2. If loading the patch bundle from an MCU, you only need the low region. See this thread for further detail: https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1194546/tps25750-mcu-memory-requirement

    3. Low region only should be sent when using PBMs.

    4. Send the patch data over I2C, then use PBMc after all data is finished transferring over I2C. Figure 4-1 in the previously reference TPS25750 TRM shows this in detail: https://www.ti.com/lit/ug/slvuc05a/slvuc05a.pdf

    5. Here is a document going over how to use patch burst mode over I2C: PBMs_4CC.pdf

  • For item no.5, I saw there are a couple of code snippets provided for the patch bundle update, are you able to provide the full example codes?

  • I will see if I can find any full examples and get back to you by EOB tomorrow.

    Kind regards,

    Conner Gillette

  • Hi, any update on the full examples?

  • I need to clean up the code, but I should be able to provide it to you by EOB on the 31st.

    Kind regards,

    Conner Gillette

  • Hello any update of the full examples?

    Though I am trying to write my own codes to exercise the patch bundle update flow. But i have encounter a couple issues as below:

    1. What is the sequence of sending the 4CC bytes? Using PBMS example, the i2c data contains "i2c_addr, reg_cmd_0x8, length_4, P, B, M, S"? sending the 'P' or 's' first?
    2. The first byte return data of the 0x9 register always give me 0x40, is that the correct value? I read some document somewhere following the PBMs command, the first byte return data is 0x1 indicating one length of data byte available?
    3. I used the 0x10 as the input DATA1 slave address for the PBMs commands, but subsequently when i send the i2c write command of to this 0x10 address, I am getting i2c NACK. ( the PBMs is sent successfully by examining the CMD & DATA register, there is no !CMD and no error ).

    Thanks.

  • Using 4CC Commands (3).pdf

    Here is a document on using 4CC commands over I2C and examples. This should fix your ACK issues.

    What is the name of the 0x9 register? I do not see it in the technical reference manual.

  • The document does not help with the ACK issue. The 0x9 is the DATA1 register as per the reference manual.

    Are you able to provide the full code examples?

    For the NACK issue, below is my steps (the slave address is 0x42):

    1. Read MODE register data ( 0x3 ) data return is 0x4, 'P', 'T', 'C', 'H'. ( first byte is len, subsequent is PTCH ):
      1. i2c address 0x42
        Data[0]: MODE Register(0x03)
        Data read:
        ReadData[0]: BYTE CNT (0x04)
        ReadData[1]: 'P'
        ReadData[2]: 'T'
        ReadData[3]: 'C'
        ReadData[4]: 'H'
    2. Send DATA1 register data ( 0x9 ): 
      1. i2c address 0x42
        Data[0]: DATA1 Register(0x09)
        Data[1]: BYTE CNT (0x06)
        Data[2]: BundleSize[7:0]
        Data[3]: BundleSize[15:8]
        Data[4]: BundleSize[23:16]
        Data[5]: BundleSize[31:24]
        Data[6]:SlaveAddress (0x10)
        Data[7]: TimeoutValue (0x32)
    3.  Send CMD register data ( 0x8 ):
      1. i2c address 0x42
        Data[0]: CMD Register(0x08)

        Data[1]: BYTE CNT (0x04)
        Data[2]: CMD STRING ('P')
        Data[3]: CMD STRING ('B')
        Data[4]: CMD STRING ('M')
        Data[5]: CMD STRING ('s')
    4. Read CMD register data (0x8 ), data return is 0x4, 0, 0, 0, 0 ( first byte is length of 4, subsequent 0 is command ok? )
      1. i2c address 0x42
        Data[0]: CMD Register(0x08)
        Data read:
        ReadData[0]: BYTE CNT (0x04)
        ReadData[1~4]: 0
    5. Read DATA1 register data ( 0x9 ): data return is 0x40, 0 ( first byte is length of 64, subsequent 0 is data ok? )
      1. i2c address 0x42
        Data[0]: DATA1 Register(0x9)
        Data read:
        ReadData[0]: BYTE CNT (0x40)    //  is this correct?
        ReadData[1]: 0                               // only read one byte as the task response?
    6. PMBs sent successfully. Start burst write data
    7. Send burst write data to another slave address 0x10 ( as this is used in step 2 above ):
      1. i2c address 0x10
        Data[0]: patch data

        Data[...]: patch data

    8. I2C function return NACK error. From the oscilloscope, the slave address 0x10 is NACK, there subsequent patch data does not get send out.

    Questions:

    1. Any of the steps data or interpretation above is incorrect?
    2. Is step7 using the slave address 0x10 which is specified as part of the DATA1 input for the PBMs command correct?
    3. Does the first byte of the data read from the register DATA1 ( 0x9) in step 5, represent the length of the data or it is the actual task response?
  • I will review your steps and provide an update by tomorrow, EOB.

  • What is your ADCIN configuration? I need to check and make sure your I2C addresses are correct.

    Kind regards,

    Conner Gillette