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Hi,
I have a power rail requirement of below
Polarity | Voltage | Load Current | |
+ | 2.5 | 400 | mA |
- | 2.5 | 400 | mA |
+ | 5 | 620 | mA |
- | 5 | 330 | mA |
In my current design i depend on non-TI solution where i use a 12V to multi rail buck converter, the converter output is filtered through a CLC filter, with combinations of 0.1uF,4.7uF,0.01uF,47uF
the output then taken to a LDO again the LDO output is maintained with a CLC filter
But still my output is noisy like below
-2.5 Rail
-5V Rail
a wide snap of -2.5v rail
similar nature with the positive rails also
Effective the noise is arround 100mV Peak to peak
i have a amplifier signal chain to which this creates serious problem and i am unable to reduce the reference voltage of A/D conversion due to this problem
Below is my signal chain
Kindly suggest a power solution for noise sensitive applications like FSO,LIDAR etc.
Hi Shyam,
We create very few PMICs with negative voltage outputs. The PMIC devices we do have with a negative voltage output are TPS65530A and TPS651851. Unfortunately, the TPS65530A only has one inverting output, and the TPS65185 cannot support the current requirements.
You may be able to find discrete devices using our Buck-boost & inverting regulators search tool or Webench Power Designer that will fit your use case. Additionally, the Mechanically scanning LIDAR block diagram can suggest additional components useful in LIDAR applications.
Regards,
Megan
i have faced many problems with PMIC, i am not looking for a PMIC solution in this case
The rails can be from individual ICs , where i have flexiblity to adjust output so that i can use same regulator and DCDC for all requriements
web bench suggests many but my real bottle neck of slection comes picking the DCDC + LDO solution which offers very low output ripple and noise.
though my solution is for LIDAR, i am making a generic reciever module targeted light pulse applications, where the trade off after power is noise only.
my needs to work at ultra low noise conditions is what my search paratmeter is, i am ready to spare BOM cost and Effeciency also, but i need the ultra low noise and ripple performace, which tools may not properly slect
For example for input parameters fed, solutions are suggested whose output noise is in 20-50mV, what i am looking for is in uV range !
because if the power noise after coupling opamp , it amplifies it to alteast 500mV, that is what i am facing currently as a problem.
Hi Shyam,
Maybe TPS63710 inverting Buck-Boost https://www.ti.com/product/TPS63710 + negative LDO is a good solution.
Regards,
Bryce
I came across TPS54120RGYT which is with internal LDO is there a equivalent for -Ve voltage similar to that ?
Also coming to ripple and noise how would you compare TPS54120RGYT with a sperate DCDC and LDO solution ?
Is there any improved solution to TPS63710 with integrated LDO ?
Hi Shyam,
We have TPS62913 which can be used as (IBB) inverting buck boost converter and support low noise and low ripple in the meantime.
It's not a Buck-Boost + LDO solution. TPS62913 can directly support low noise and low ripple application which are ideal for noise sensitive applications that would normally use an LDO for post regulation such as high-speed ADCs.
You can refer to below notes for further information.
https://www.ti.com/lit/an/slvaew7/slvaew7.pdf Powering Sensitive ADC Designs with the TPS62913 Low-Ripple and Low-Noise Buck Converter
https://www.ti.com/lit/ug/slvuc22/slvuc22.pdf TPS62913 Inverting Buck Boost EVM User Guide
please let me know , how you will compare the integrated solution TPS54120RGYT with suggested one, except efficiency
these are too many options its quite confusing, which one to go for
1A solution looks ok for me, but i need best, let me know the best one so for noise and ripple, on top if its integrated it would be great
TPS62913 is a solution with output LC filter, should i need to incorporate one more LC filter to reduce noise to uV level from mv level ?
Hi Shyam,
Sorry for missing the comparison.
TPS54120 is suitable for your positive output voltage application but it can not support your negative solution considering the low ripple. Also it's an old part released in 2012.
TPS62913 can not only support your positive output application but also can be used as IBB for your negative output application. Also TPS62913 is a integrated device with better low noise and low ripple solution released in 2020, so I think TPS62913 is the better one.
TPS62913 is a solution with output LC filter, should i need to incorporate one more LC filter to reduce noise to uV level from mv level ?
Yes, you need a 2nd LC filter for TPS62913. Usually the 2nd inductor is a ferrite bead.
i think 62913 is only for positve output, please check again the Vout min is 0.8v only, i could not find application note explaining the usage for -ve output.
Hi Shyam,
Please refer to this EVM user's guide to use TPS62913 as Inverting Buck-Boost and support negative output.
https://www.ti.com/lit/ug/slvuc22/slvuc22.pdf TPS62913 Inverting Buck Boost EVM User Guide.
Thanks for the quick response, i need to place a LDO after this right
can you suggest a ultra low noise High PSRR LDO after this stage ?
Thanks for looking at the TPS62913 for this application, and thanks for looking at the app notes I've written for these types of applications. Although the TPS62913 can be used in an inverting buck boost configuration, if you find it has more ripple and noise than you can tolerate, there are two more options.
1) add an LDO capable of the negative output voltage, or
2) Use the TPS63710 low noise inverting buck.
Here is the 12VIN to -2.5VOUT 400mA design using the TPS63710: https://webench.ti.com/appinfo/webench/scripts/SDP.cgi?ID=B34D7D848AB5E8D0
For the -5VOUT design, you need lower than 12V input, but the input still needs to be larger than the maximum dropout of the converter.
Hope this information helps.
Steve Schnier I would go forward with TPS62913 with LDO after it, i found a variant TPSM82913, which i feel is equivalent with less footprint, so i shall go for LDO after it, Can you please suggest both positive and negative output LDOs with high PSRR and low noise ?
Athos Zhao For negative voltage i shall use same TPSM82913 but how to configure it for negative voltage ? Also kindly suggest a LDO after TPSM.
Hello,
The TPSM82913 has an internal cap from VIN to GND, which is not recommended for the inverting buck-boost configuration. You can still use it, but would need to add a zener diode to the output, which would take away from the space savings of the module. It is a good option for the positive output rail.
Steve Schnier can you please suggest me the low noise high PSRR LDO for both positive and negative outputs after DCDC.
Hi Steve Schnier i did not see anyone coming back , kindly resolve the LDO issue please, i have found TPS7A88 being used for sensitive applications, you may throw some light, i need help in identifying similar LDO for negative voltage also
Hi Shyam,
We have options for you. The TPS7A88 is good but we can do much better. Please review the switching frequency you are trying to filter and assess if the PSRR in these curves will work or if you need even more PSRR in your system. Let me know if you have any questions at all.
Positive LDO - TPS7A94
The industries lowest noise LDO is the TPS7A94, which is a positive rail output and can deliver 1A of current. It can provide 0.47 uVrms of noise from 10Hz - 100KHz (this frequency span is the industry benchmark and allows you to compare noise across many LDOs quickly and easily). Shown below is a PSRR curve for the TPS7A94 at 3.3V output (I didn't see one specifically for 2.5V in the datasheet but the results will be similar).
The TPS7A94 was designed to be paralleled and this brings you many benefits including even lower noise. This is because each LDO that is paralleled looks like an uncorrelated noise source to the next paralleled LDO. Uncorrelated noise sources connected in parallel have a net reduction by the square root of the number in parallel. So by paralleling 4 TPS7A94, you can reduce the 0.47 uVrms by a factor of 2, and so forth. Another benefit of paralleled LDOs include higher system PSRR without dissipating more power. As you can see in figure 6-3 above, LDO PSRR goes down with load (this is common to all LDOs). If you need more PSRR at a specific frequency such as 100kHz, we can parallel the LDOs so each LDO delivers a fraction of the load current which raises the system PSRR.
Negative LDO - TPS7A33
We also have a low noise negative LDO. The TPS7A33 has 16 uVrms (from 10Hz to 100KHz), high PSRR and 1A of load current. This LDO can also be paralleled to achieve the same performance enhancements I described earlier.
If you decide you want to parallel the TPS7A33 to obtain lower noise or higher PSRR, I would recommend paralleling the TPS7A30. The TPS7A30 can only provide 200mA of load current but has slightly lower noise (15.1 uVrms). The TPS7A30 is half the price of the TPS7A33, so if you find you must parallel to reduce noise and increase PSRR, it will be cheaper to use the TPS7A30 over the TPS7A33.
Brand new tools for parallel LDOs
If the specifications of these LDOs by themself work for you and you don't need to parallel LDOs to achieve higher performance, you can skip this section.
Parallel LDOs have really increased in popularity for many reasons, so we have recently developed new collateral to help you with your design. Using the PARALLEL-LDO-CALC MS Excel tool, you can quickly enter your system requirements the tool will immediately output the number of parallel LDOs required along with the minimum ballast resistance needed. The tool uses worst case analysis in its solution. There is no VBA in the tool so most engineers should be able to download it.
If you want to learn more about the theory of parallel LDOs, here are 2 technical white papers.
Parallel LDO Architecture Design Using Ballast Resistors
Comprehensive Analysis and Universal Equations for Parallel LDO's Using Ballast Resistors
Thanks,
Stephen
Thanks For your response, i wish to go for review of my design, shall i post here or shall i open a new thread ?
Either will work. If you post here then I'll get the email notification. If you open a new thread for LDOs, that is fine too - I'll watch for it.
If you could provide your specific requirements for noise and PSRR I can verify those are being met.
Thanks,
Stephen
thanks for responding, i want to reach as low as possible electronically, so that i can achieve better SNR from existing design
as i have said in question description, currently i use a LT DCDC followed by CLC filters > then followed by a LDO> again followed by CLC fitlers, for which i am seeing 100mV noise at output of Op-Amp even if there is no signal applied, the scope shots are posted in main question.
i wish to reduce the switching noise at opamp output as much as possible in amplitude.
because of this noise i need to keep my reference to atleast 500mV for safe A-D conversion of signal from photo diode
if noise of opamp-ouput is reduced much further it would help in improve my SNR.
also i am confused on which switching frequency to use my photo diode signal is of range 1Mhz to 100Mhz
Hi Shyam,
Okay I can help. And we should be able to get you the lowest noise solution possible, don't worry about that.
When we say switching frequency, we mean the switching frequency of the LT DCDC switching converter. What is the switching frequency and ripple voltage of the LT DCDC? To know what this is, you'll need to review your LT DCDC analysis and let me know. As an example, let's say the LT DCDC is 1mVpk ripple at 100 kHz. And let's further say that you want 1uVpk ripple at 100kHz after the LDO. This means that the LDO needs 20*log(1000) = 60 dB of PSRR at 100 kHz to meet this requirement (which we can easily show that the TPS7A94 meets this with the PSRR curves, but this is just an example).
If you are new to DCDC converters, it may be easier for us to recommend a DCDC converter but that means you'll need to remove the LT DCDC and insert a TI DCDC. Let me know if you are open to this and we can loop back our DCDC team. In either case I'll still help you fully with the LDO post regulation for the lowest noise possible.
It is also helpful to know your photo diode signal range is 1 MHz to 100 MHz. Do you expect the LDO load to be steady state (like in your table of load currents) or do you think there will be load current transients? If the load is steady state then we can add a series ferrite bead and shunt capacitor to reduce the noise and improve the PSRR even further.
TPS7A94 Noise with an LC filter on the output
Thanks,
Stephen