TPS50601A-SP: SYNC pulled high

Daniel,

Daniel Hartung said:

Pulling SYNC high will cause the device to believe there is a clock on the input, and likely cause the device not to switch at all.
The SYNC switching later would have the device move over to that clock.

Indefinitely? For a duration of 20us?  Does this require a reset? (i.e., pulling EN low) --- see link below.  

TPS50601-SP: Synchronization Timeout - Space & High Reliability Forum (Read Only) - Space & High Reliability (Read Only) - TI E2E support forums

Kyle stated "The only caveat here is that after the oscillator is disabled and if for whatever reason the external clock is no longer provided, the device will not go back to using the internal oscillator."  (I bolded the key words that have caught my attention here....)

Does this mean that the internal oscillator is not receptive (a.k.a. not listening) to events such as a sudden loss of an externally provided clock? 

Is this contingent upon whether or not the external clock was provided before or after the 20us period? (From the way I am understanding, the internal oscillator is highly depended on whether that clock was received before or after the 20us listening period.)

What would this look like if the TPS50601A was already running without a SYNC signal and then at a later time, the SYNC signal was provided but periodically drops out and comes back up from time to time?  Can the TPS50601A successfully resolve the decisions between the external vs internal clock without experiencing any SLOP or spurious responses at the output?

For the EN pin, we provide the same 5V output as VIN/PVIN with a divider to set UVLO.  Currently we have a pull up to ~5V through 2k to the SYNC which occurs before power is being applied to VIN/PVIN and EN.

The questions above pertain to two cases both possesing the topology to utilize the external SYNC signal: (1) SYNC pulled high before powering up the IC and continues to remain high (with power down following the reverse order) and (2) SYNC signal provided before (or even potentially after) the 20us listening period.

I'm aware of the 10k (or 1k for reducing SEE) being tied to ground to utilize the internal oscillator.  Does the +/-5% tolerance play a role in interchanging between external vs internal?

TPS50601-SP: SYNC Pin pull down resistor - Power management forum - Power management - TI E2E support forums

Thank you,

Ben

Hey Daniel,

Thank you for the expedicious response.  

Regarding this statement,

"I just went through and tested it by constantly applying and unapplying a 100 kHz clock signal and the TPS50601A-SP SYNC pin on our standard EVM as it was running and saw it change clocks consistently."

Upon removing the 100kHz clock signal, is it uneffected by this being either pulled high or tied low triggering the change from external to internal?

Thank you,

Ben

Hey Ben,

I checked pulling the pin high while the device was running as well and then switching back to an internal clock.
The device switched over to the internal clock appropriately.

Thanks,
Daniel

So in essense the SYNC pin is considered 'cold sparable'?

Hey Ben,

Could you please provide a definition of 'cold sparable'

Thanks,
Daniel

"The worry here is if the TPS50601A-SP has the SYNC stay high and the EN turn on, you can end up in a situation that the device has gone through start-up, but never actually switched.
This is something that would need to be planned for in the design as a whole."

Could you elaborate on this?

What do you mean by 'planned for in the design as a whole'?  Are you insinuating that a need to set an external UVLO above the 2.75V threshold is required? 

The datasheet shows that the internal UVLO is 2.49V and 2.75V for PVIN and VIN, respectively.  If a pull-up (5V with or without current limiting) were applied to the SYNC pin and then the IC were powered up and down at VIN/PVIN, can it result in internal sequencing issues (assuming ideal values at other pins for simplicity)?  What if it was provided an external sync?  If it wasn't?  Furthermore, does a minimum load applied to VIN/PVIN prevent this from happening with a current limited pull-up at SYNC? 

On the EVM board 5V applied to the SYNC pin (without current limiting) results in 2.9mA of current flowing into the SYNC pin and 2.71V at VIN/PVIN.  When loading down VIN/PVIN with a 1.5kΩ resistor, the current increases to 3.9mA at the SYNC pin.  If current limiting (e.g., 2kΩ in series with the SYNC pin) were applied to this circuit, is it preventing an overstress or latching condition when going through power ups/downs?  (Assume that the EN pin had a divider with a UVLO setpoint much much greater than the internal UVLO threshold for VIN and PVIN).

Daniel Hartung said:

Could you please provide a definition of 'cold sparable'

By that I mean can voltages can be applied to the devices I/Os before and during power-up which do not result in the following: (1) tri-stating the I/Os before/during power-up, (2) applied voltages to the I/Os must not power up any part of the device, (3) device reliability must not be compromised if voltage is applied to I/Os before or during power-up.

Is there any clamp(s) in place to prevent either the entire device or portions of the device from powering up when a voltage is applied at the SYNC?  (Assume the voltage range across the absolute maximum based on the data sheet of -0.3 to 7.5V)

Hey Ben,

I will give an explanation for how the SS works in the part:
The device once enabled changes the SS capacitor and uses it as a reference for the SS period.
The device finished the SS period and switches over to the internal reference no matter what is happening externally, unless something would cause it to go through restart.
The device doesn't make sure the output voltage comes up, or delay it if there is a change in clocks part way.
The SS time finishes regardless.

The worry here being if there was a strange signal on the SYNC pin that was misinterpreted as a clock, but didn't actually switch the part enough to bring the output voltage up, you would not have the SS period of the part and cause non-linearities at start-up.
This being said, a consistent pull up resistor wouldn't cause switching on the pin and thus shouldn't cause that issue. (See two paragraphs down)

As far as your second post:
(2) and (3) the device is fine with (1) is a maybe.
Perhaps listen to my explanation and make your own decision.

The TPS50601A-SP when the SYNC pin is configured as an input "listens" to the SYNC pin to override it's own clock.
Applying a random voltage to it could have some strange side effects if you gave a signal that the device could misinterpret as a clock.
The device as a whole looks for edges in order to "see" it as a clock.
This is why the initial pulse from a 5 V signal might get misinterpreted, but as long as it doesn't keep switching the device changes over back to its internal clock.

The device needs power on VIN/PVIN to power up.
Voltage applied will only effect the device when it has power on the power pins.
The SYNC pin itself doesn't apply voltage to the part, nor does it have the internal ESD diodes that are referenced to an internal node limiting the voltage on the pin.

Thanks,
Daniel