UCC21222: Practical limit for a long Deadtime ?

Hi Vlad,

This is a noise sensitive pin even for 100ns deadtime setting. But we are in the process of releasing an update to this device; the first version of the update is UCC21551 and has samples available now, but different versions will be released later in the year. It will have greatly improved internal filtering of the DT pin and will allow you to set deadtime more accurately out to a longer interval.

With a 100nF external capacitor, the highest setting specified is 500ns, but I have seen it used up to 2us. I have not measured when it becomes effectively open circuit and when overlap is determined by the inputs. I can try to test this and get back to you.

Usually automotive customers have internal rules against resistors over 200k, due to long term reliability.

Best regards,

Sean

Thank you Sean for reply.

I'd appreciate if you can confirm from your tests that we can reliably make at least 2uS DT (or more?), assuming a clean implementation, bypass caps to DT resistor and also to the chip' VCCI and close components positioning to the chip' pins)...

Otherwise looks like I am in trouble now. I need to cover for the long delay of the high side MOSFET gate capacitance discharge, while turning OFF,    overlapping with fast turning ON on the low side... so a too short DT will not prevent a possible shoot through ... if I cannot get enough DT time, we need to change the design of half bridge.

Please let me know.

Vlad.

I just found another similar product from TI :   UCC21320Q

Hi Vlad, 

Sean is currently OOO for holiday, he'll get back to you when he returns. I do have a question in the meantime regarding the high discharge - 

Vlad Blanshey said:

I need to cover for the long delay of the high side MOSFET gate capacitance discharge, while turning OFF

What is the gate capacitance of the HS FET, the external gate resistance of the HS FET, and the turn-off time you're seeing? With UCC21222 or UCC21320's 6A peak sink current, we usually see pretty fast fall time for FETs.

Thanks! 

Best, 

Vivian

Hi Vivian, our high side P-mos in H-Bridge is not directly driven by the driver' output but after the N-mos inverter which in turn driven by the driver. This inverting N-mos works fast , does not introduce delay but the charge and discharge of the P-mos depends on the current from the dividers of the main bus voltage and that's quite limiting (power dissipation of the dividers), I cannot increase the current for the P-mos gate to such a degree that to limit the discharge time below 3 uS.

But this is different topic. The topic here is how to get a dead time setup at least 3uS ? Again, TI datasheet for UCC21320Q spells out max DT resistor 500kOhm - this would make a 5uS DT. How did TI come up with this value? was this tested? And again UCC21222 having the same DT range? datasheet does not even mention the allowed range for the DT resistor.

I think that all the datasheets for the gate drivers, if they have a DT feature, must spell out upfront the practical limits of the produced DT . Currently all the developers are left to do their own research to find out this missing parameter in datasheet. (To be fair this applies to many manufacturers of the gate drivers).

Hi Vlad, 

Thank you for your information. I'll let Sean comment on the DT range after we return from the holiday. 
Best, 

Vivian

Thank you Sean, your test is very important for me to make the final decision. May be I can try to make a clean setup for 1uS DT.  Your referrals to other drivers from TI are confusing though.

• The new UCC21551 chip I checked datasheet - allows only up to 100K DT resistor which translates to only 873nS max and even shorter DT than UCC21222 with this resistor (1uS). (This chip is not even available)
• The UCC21320QD chip I mentioned before under consideration allows up to 500K which translates to 5uS according to a datasheet. The question remains : can this info be trusted? (This chip we can get)
• The UCC21530 you mentioned is no different from UCC21222

I cannot play with input signals because they are produced automatically from the MCU' embedded timers as a response to the input from the sensors. If sensors get messed-up, the produced controls of H-Bridge might be messed-up.

As for the H-Bridge design , I started from a "classic" design with N-mos high side and bootstrap cap and it was a mistake because we don't use PWM for H-Bridge control. There is no switching to pump-up the bootstrap capacitor after reset, yet the state of H-Bridge must turn ON for a requested input.

I still hope to get more info from you on the UCC21320QD . Even if mentioned 5uS derived from it's spreadsheet is too much to ask, still it may allow a more reliable DT than all of the above.

Thanks again,

Vlad Blanshey

Hi Vlad,

 The UCC21551 is brand new this week, and all of the first batch was quickly picked up for samples. It is made on a 300mm wafer in our new fab, so in the near future it will be much more available and cheaper than the UCC21530. I would like to emphasize that it is also a much improved design based on customer feedback from the UCC21530. 

It makes sense that the signal source is not so easily manipulated. Just an observation from my testing. Are you able to add deadtime in your software? There is a setting in the InstaSpin sample code for deadtime, if you are making a motor controller. I recall I was able to set 2us, and I don't think that there was an upper limit.

Bootstrap is only the simplest, cheapest option for powering the high side driver. The best way is to use an "isolated bias supply" or isolated DC/DC converter. It is essentially a small flyback converter, alternatively push-pull, maybe plus a secondary LDO, that is referenced to the switch node. It floats on top of the switch node and powers the high side isolated driver regardless of PWM. This also provides galvanic isolation. Most people use a discrete solution using something like the SN6501 and and LDO, but TI has a whole product line dedicated to this function, as well as an E2E form. UCC14141 is an example of an integrated solution.

While the UCC21530 datasheet might say 5us, I have seen lots of noise problems with the UCC21320 deadtime even at much lower values. I think it is just a design limitation due to decreasing current input signal and constant noise. I don't think that it will indeed have a longer usable deadtime than the UCC21551.

 Best regards,

Sean

If I understand correctly from your info, all those UCC21320, UCC21530, UCC21222 and probably new UCC21551 drivers suffer from the noise on DT resistor input pin due to the same reason - all have very low sensed current (10uA and below if longer DT) . In that case replacing our current stock of UCC21222 will not help.

I don't understand the approach you suggested with isolated floating power supply while using N-mos for the high side of H-Bridge. We already use isolated (from MCU power) DC-DC converter for the H-Bridge and for output of UCC21222 driver but I don't know how to use N-Mos for that without a bootstrap cap. Any AppNotes from TI on this solution ? I didn't see a reference to such solution in my "Bible" appnote from TI (see below) or, may be I didn't understand it's description if it is there.

Yesterday I ran the spice simulation on the updated high side switch using the complementary BJT driving the gate of P-mos. This is a suggestion from the TI's "Bible" on the MOSFETs gate driving solutions  Fundamentals of MOSFET and IGBT Gate Driver Circuits . My discovered solution is in Fig. 20 . ( I read over this TI's Appnote like a Gospel study in Sunday school )

Once I included this complementary BJT pair onto the gate circuit, the discharge of the high side gate' capacitance was reduced to 1.5uS . I can easily tune up the turning ON of the low side MOSFET to the same delay , whence switching OFF of high side vs turning ON low side will have the same delay! In such case, to prevent a shoot through, the required DT can be as low as 1uS (100kOhm DT resistor) or may be even lower only to ensure any real life discrepancy (for ex. MOSFET' gate switching threshold changes from the temperature...).

Looks like we'll be able to use our current stock of UCC21222 and in the future get UCC21551 (when available) even if no fundamentally different but may be somewhat better resistance to noise.

Thanks for help

Vlad Blanshey

I probably came to understand your suggestion regarding using N-mos for the high side of H-Bridge without PWM inputs. Is it suggested in Fig.21 of the Fundamentals of MOSFET and IGBT Gate Driver Circuits ? If it is, - I dropped it from consideration . It's gate switching at the MOSFET source is greatly effected by the EMF from the inductive load - a big headache to deal with.

Hi Vlad,

The UCC21551 will have a de-glitch filter on the DT setting to help with noise. It will still be sensitive to low frequency noise, but it's still a lot better than those previous devices.

That app note is indeed a Bible! I built my first motor inverter off its precepts, and I hope to one day meet Lazlo at TI. He is essentially a CTO now.

I wonder if a low power "isolated bias supply" is a new technology since his app note was written. I just transferred to this group this year (from HSAMPS), and many customers do power their high-side isolated gate drivers with an isolated dc-dc. Here is an overview presentation (<-link) on different types. The most common is "semi-distributed", where you use one transformer for 4 flyback outputs: one output for all the low side drivers, and one for each high side.

It eliminates the need for a PWM, supports negative turn-off (higher switching speed and Miller protection), and also protects against high-side Miller turn-on during start up, vs. a bootstrap.

Basically an "isolated bias driver" is an additional isolated DC-DC supply that is just for each high side driver, and replaces each bootstrap capacitor. No, Figure 21 is something else. I don't think that this will work for a very high "Vin". 

 BJT totem poles will have stronger drive strength at the gate Miller plateau due to their higher gm. TI just can't integrate them into a gate driver on a low-cost 300mm CMOS wafer. 

I still think there is benefit in lower Rdson with an NMOS instead of a PMOS, and you might still want to consider an "isolated bias supply", but I am glad that you found a solution that works.

Nice to meet you and good luck with your design.

Best regards,

Sean

Yes, de-glitch filter is good to have for DT resistor... at least that much protection from the noise if it is so hard to make higher amps flowing into the DT measuring pin to reduce the noise I will watch to see when  mouser.com gets them in stock to order in the future. Meanwhile as locals say here "If it's ain't broken, don't fix it."  Can continue with UCC21222... Now, playing with resistors values in spice and using totem-pole BJTs at the gate, I got the switching OFF delay lower that the lower side switches ON !  So thanks to the solution from that AppNote (Please say "thank you" from me to the author if you know him), the additional protective DT time can be low enough to be secured by UCC21222

Thanks again

Vlad