TPS650864: Can't get Buck 1 working

Thanks for the reply James. 

My apologies. When I stated "pulled HI" I just meant removing a jumper which pulls CTL4 low (I wanted to test LDO5P0 and LDO3P0 before enabling any Bucks).

CTL4 (and all other CTL lines) is pulled HI with LDO3P0 exactly as is done in the TIDA-01393 schematic. Is it possible the oscillations on Vsys could be caused by Buck 1 failing?

Took another look. I get the same scope capture even if I don't enable BUCK1 (CTL4 is held low)

Hi Craig,

Can you share your schematic and layout? (I can set up a private message space if needed). Even if the design is based off the TIDA board, I would like to have a copy of your board documents.

1) If you use a larger input voltage (8V for example), do you still see the ripple behavior at the end of the ramp up?

2) Can you swap the IC to a different board to see if the issue follows the chip or the board?

Regards,

James

I tried it with higher Vsys. No difference. even the ripple voltage (~850mVpp) stayed the same.

We have two PCB's, and they both share the same characteristic (including no BUCK1)

We can definitely share the design in a private space. Any particular file format of the layout? It was done in Altium.

Hi Craig,

Please accept my friend request and I will open the private chat for file sharing.

For the schematic, PDF format would be the best. For the layout, Altium files would be fine.

Was the order of events the same on both boards?

1) Power-up board the first time and see correct BUCK1 voltage (5V) after pulling CTL4 HIGH

2) Shut down board fully

3) Power-up board again but now VSYS ripple is present and BUCK1 does not regulate correctly

4) FB resistance drops to low impedance to GND

Regards,

James

I added you as a friend. and yeah, that's pretty much what's happened. Not sure if the feedback pin failed right away, or from my poking around, but they both failed.

Hi Craig,

I will take a look at the schematic and layout and get back to you within 3 business days. I would also like to grab some scope captures of our EVM for comparison. I have a large amount of lab testing going on at the moment.

Regards,

James

Thank and much appreciated

Hi Craig,

No problem, I'll update you once I have more to share.

Regards,

James

Hi James

I received my PCB after getting the TPS6508641 replaced and I have some outputs!

I have LDO3P3, LDO5V0, Buck1, 2, 5, 6, SWA1, and LDOA2 all functioning.

I DO NOT however have Buck 3, 4, LDOA1, LDOA3, or SWB1/2.

I have CTL 2,3,5,6 all pulled high from LDO3P3. CTL1 is held low.

GPO1 is low as well, which I think it should be set hi if buck1 is good.

Hi Craig,

Thanks for the update. I didn't see anything that stood out as problematic in the schematic. I still need to take a look at the layout but given your recent information there's a few other things we can also check more immediately.

Can you provide a full readout of your register data? In particular, registers 0x05, and 0xB2 through 0xB6  are status registers that report on the PMIC behavior. These registers have bits that are latched into memory and will persist until you write 1b to the bits to clear them.

Checking these registers may provide further insight into any potential power faults or issue stopping the full power up sequence from completing.

If you are using TPS6508641, GPO1 is configured for "open drain" which means you will need a pull up resistor to either 1.8V or 3.3V.

Regards,

James

I'll do get a register readout. I realized that GPO1 and 4 need to be tied hi last night as well.

Hi Craig,

Understood, let's see if the GPO1/4 fix changes the behavior and check the registers.

Regards,

James

Sigh....

I can read  the registers if CTL4 is kept low, but not if the device is running. I verified this by reading the ID registers, 0&1. If CTL4 is low I read 0x10, & 0x24. If CTL4 is hi (I have the above outputs active) registers 0&1 return 0x00

All I got  is my 0.72V output and the switched .85 output. No extra voltages. One thing I don't get is how does GPO4 go active when I don't have BUCK4? According to page 35 of the data sheet, GPO4 is active when Buck4 goes hi (like a power good)

Hi Craig,

If you are encountering a power fault after pulling CTL4 high, you should still be able to read registers 0x05 and 0xB2 through 0xB6 once I2C comes back up since the bits in these registers are latched.

What do these registers say if you keep CTL4 low and perform a read?

Regards,

James

Register

0=0x10, 1=0x24, 5=0x04, B2-B6= 0x00

I tried writing a zero to reg 5, but it doesn't seems to take....

Hi Craig,

Based on those register readings, it doesn't look like the PMIC is reporting a fault. 0x04 in register 0x05 indicates that the PMIC was shutdown by UVLO but this is normal if the device is turned off by removing main power.

Before you mentioned that you were getting good power output up to LDOA2 in the sequence but now it sounds like you are not getting any power output from the PMIC itself and I2C is is unavailable as a result.

1) Did this happen after you added the pull up resistors to GPO1/4? Did you change anything else between the partial power up to LDOA2 and the current situation?

2) Are you seeing issues with VSYS, LDO5, or LDO3P3 like in your original post?

3) If the registers don't give an easy answer then we need to look at the power up sequence on the scope again. Can you get some scope captures showing the rising edge timings for the power up rails starting at VSYS and working through the power up sequence? Make sure to specify the time scale and label the signals.

• Capture 1: VSYS, LDO3P3, LDO5, CTL4
• Capture 2: CTL4, BUCK1, BUCK2, BUCK5
• Capture 3: BUCK5, BUCK6, LDOA2, BUCK3

Regards,

James

HI James.

Sorry for the confusion. I am still getting voltages upto and including LDOA2, but I am unable to read the I2c when the PMIC is active. I can only seem to read i2c when it is inactive (CTL4=low).

I have LDO3P3, LDO5V0, Buck1, 2, 5, 6, SWA1, and LDOA2 all functioning.
I DO NOT however have Buck 3, 4, LDOA1, LDOA3, or SWB1/2.

I will get the screen shots in the morning

Hi Craig,

Thanks for clarifying the current behavior. It looks like you have BUCK6 as the pull up supply for the I2C lines. Are you using a separate system to drive I2C before BUCK6 becomes available? If there are two different communication sources it's possible that one source is interfering with the other. You can probe the SDA and SCL lines to see how the rails change before and after the power-up attempt.

On your schematic, BUCK2 and BUCK3 don't have explicitly marked feedback lines coming from the positive terminal of the output capacitors. I saw that you had the FBVOUT2 and FB3 pins of the PMIC marked with the correct net names, but these nets don't appear to be connected to the output of the BUCKs. Is that intentional? Some of the other BUCKs show the feedback line in the schematic.

Regards,

James

Morning James

I do have BUCK6 pulling up the I2C lines for the final design. However, I have the pullup resistors removed on this power supply board as I am pulling up with 3.3V on my test board with a PIC on it  that is used for measuring voltages. When this power supply supply board is all vetted, I will re-install the 1.8v pull ups, so I can talk to the PMIC from my xilinx board.

Similarly, BUCK2 and BUCK3 have feed backs coming from the mating board so the feedback is from the destination point (i.e. the xilinx soc). Currently they are net tied on my test board (that measures all the voltages). This was setup to match the design of the xilinx pcb that WILL be paired with this power supply.

Here are the screen shots. very interesting, especially BUCK5 and LDOA2. It appears as though they are resetting periodically, which may explain why my I2C is not functioning properly.

tps6508641 Scope Captures.pdf

Hi Craig,

Thanks for the scope shots. LDOA2 looks the strangest out of all the signals so I took another look. I don't see any output capacitors on LDOA2, LDOA1, or LDOA3. The outputs should be bypassed to GND with a 4.7uF capacitor.

For the TPS6508641, these LDOs are all enabled when you pull CTL 4,2,3,5,and 6 HIGH. Even if the outputs are not being used to drive an external system, the output capacitors are still necessary for stability.

I will link the schematic checklist I use when looking over the outputs. There are a number of different checks but the scope captures narrow things down in most cases: TPS65086x Schematic and Layout Checklist (Rev. A)

This is found on the product page for TPS650864x.

Regards,

James

Morning James

Sorry for the delay.

Great catch on the 4.7uF cap. I have them on my xilinx board, but not on the PS itself. I added some 10uF (all we have in-house) and I got outputs! I have everything except for LDOA1, LDOA3, and SB1_2. It is possible that replacing the PMIC IC wasn't a 100% success... Any ideas on the lack of SWB1_2? LDOA1 and 3 , I don't actually use in my design.

In case I haven't mentioned it before. thanks for your help. it's been invaluable.

Craig

Hi Craig,

I'm glad the suggestions are working for you! Sometimes these issues can be hard to track down but it looks like we are on the right track.

Regarding SWB1_2 not coming up, are you still seeing the repeated reset behavior or small dips in output power voltage? SWB1_2 should be enabled as long as CTL5 is pulled HIGH and BUCK4 has reached PGOOD threshold.

LDOA3 is also tied to CTL5 so you will need output caps on LDOA3 to avoid resets due to instability. LDOA1 is enabled by CTL3 HIGH so you only need capacitors on LDOA1 if you plan to pull CTL3 HIGH.

Regards,

James

Hey James

Ahha! CTL5 and 3 were inadvertently pulled low by my test pcb. I set CTL5 high and I got my SWB1_2 and LDOA3 outputs.

However, when I set CTL3 hi, I got the reset behaviour. I will take a closer look on monday. I am not using LDOA1, but it is bypassed with a 10uF cap.

Have a GREAT weekend!

Craig

Hi Craig,

Excellent, more progress. The CTL3 issue may be related to VTT since it is enabled by CTL3 and GPO2. In your schematic, PVINVTT is not being fed an input voltage and the VTT output is floating.

VTT will be enabled in the sequence so you will need use the following recommendations from the datasheet section shown below:

VTTFB will be connected to the positive terminal of the output capacitors.

Have a good weekend.

Regards,

James

Morning James. I intentionally left PVINVTT out due to the lack of JEDEC transceivers being used in our designs.  As LDOA1 is currently not being used as well. I am assuming I can leave CTL3 low?

Craig

Hi Craig,

Yes, if you leave CTL3 low you should be able to proceed without those outputs / inputs populated by external components.

Regards,

James

Morning James

. I started adding loads on the PMIC. I added a 2ohm load to Buck3 (1.1V@500mA), 3ohm load to LDOA2 (1.2V@400mA), and 22ohm load to Buck4 (3.3V@150mA). Things looked good.

Then I added a 2ohm load to Buck6 (1.8V@900mA) and the system start resetting. Same if I load Buck2 with 500mohm (.85V@1.7A) my circuit (I think) is the same as TIDA-01393. I haven't touched any of the current limit resistors as I really don't understand them!

Craig

Hi Craig,

Do the BUCKs regulate properly with larger loading amounts (smaller current pull)? The resistor values on ILIM should allow for those current targets so I wouldn't guess that this is an overcurrent issue.

If you are able to get all the rails working (without loads), can you read I2C? Or is I2C still unavailable after power up? Reading the fault registers here would be helpful to check if this is an overcurrent issue or a standard PGOOD fault.

If you load only BUCK2, what does the output voltage waveform look like at startup compared to the unloaded condition?

Regards,

James

Hi James.

Buck2 and 6 both work with a 22ohm load fine. All the rails  work without loads, and I2C is functioning. (reg b2-b6 read 0x00, reg 5 reads 0x04) . However I cannot read them when the IC is resetting.

If I load BUCK2 only with 500mohms (.85@1.7A) it appears to be working and regulating OK. 

I'll get a scope capture of the waveforms after lunch.

One note. I have modified the circuit. I originally had the CSD87381P powered from +5V (Vin). I now have them powered from Vsys(6v boost) similar to the TI design. I have not tried them with 12V.

But Buck 6 won't run by itself if I load it with 2ohms (1.8@900mA) 

Hi Craig,

It sounds like we should focus on BUCK6 first in this case. I would try a larger ILIM6 resistance, perhaps 9k Ohms, just to see if this improves the performance. If BUCK6 is still resetting after the ILIM replacement, then we can probably rule out a current limit issue and focus on something else.

In my previous replay I asked about BUCK2 scope shots but we should take a look at BUCK6 instead since BUCK2 appears to work fine on its own.

Regards,

James

OK. Will do.

Here is the BUCK2 O/P anyways. Just finished it. It looks like there are some resets at beginning until it stabilizes/

BUCK2 output.pdf

Hi Craig,

BUCK2 should be regulating to 0.85V but in the second scope capture the output is rising to ~1.8V. Is this expected?

Regards,

James

Hi James

I have the BUCK2 feedback coming from the load. I measure .85V at the the load and 1.8V at BUCK2_V85 on the PS

I tried a 9k09 at ILMN for buck6 and it works with 1.68V at the load (seems a bit low, but the feedback run is quite long) and 1.81V at BUCK6_1V8_OUT

I then tried adding Buck3, LDOA2, Buck4 loads, but it resets again

Hi Craig,

What is the current limit capability of your VIN power source? Are you able to test the 12V input to see if this changes the behavior?

Looking at the scope capture of BUCK2 that you sent earlier, the reset behavior seems to happen at the same time as VSYS experiences a voltage dip. How low does VSYS dip in these instances?

The fact that register 0xB2 through 0xB6 are showing 0x00 suggests that this is not an issue with a power rail fault. If that's the case then we need to check the for any input power dips / overloading that might be causing UVLO resets.

As a side note, our recommended configuration is to have the FBVOUTx lines terminate at the positive terminal of the output capacitors for proper regulation. I'm not sure what the limit is for long distance FB traces but pulling in these connections might improve the loop response to load changes.

Regards,

James

Morning James

We are running off a 3A 5V supply. I will try it with 12V and measure the Vsys again. As for the feedback, It was done at the destination (the Xilinx chip) to ensure the SOC has the required voltages (with it's tight tolerances). I could try jumping these feedbacks closer to the source as a test though.

Craig

Sigh.....

I fired the PCB up with 12V. Within a couple of seconds, it current limited (3,5A). I will need to investigate and see which IC failed.

I'll let you know.

Hi Craig,

Understood, standing by for now.

Regards,

James

Hey James

Still narrowing things down. I have gotten rid of the current limiting situation by eliminating my on-board +/-5 circuitry (I can look at that later)

However, I currently have...

• Buck1 = 4.9V
• Buck2 = .85V
• Buck6 = 4.6V ***    
• LDO3P3 = 3.29V
• LDO5V0 = 4.9V

All others are 0V. Also it looks like the chip is resetting again. 

I have no loads connected. BUCK6 ILIM resistor is still 9k. GPO1 and 4 are both low.

I may have smoked it again unless you can think of something else I can check. Tommorow I will re-check with a thermal camera to see if anything sticks out

Craig

Hi Craig,

There are a few lab items I need to finish today but I will look into this more early next week. My suggestion for now would be to go through the power up sequence with the scope again and look for the first signal that doesn't come up correctly or the first signal that resets.

Regards,

James

OK. Will do

Hi Craig,

So getting back into the swing of things here, is seems like we were able to get most of the rails up and running with the 6V VSYS input. However, after switching to 12V VSYS to avoid some potential UVLO conditions, now it sounds like the power up sequence is stopping half way again.

What are you seeing on the scope during the power up sequence? (Keep an eye on registers 0xB2 through 0xB6 in case power faults creep up)

Regards,

James

Hi James

Been a while....

Not sure if you got my last message or not, but I sent the board out to replace the IC again, and they sent it back with the wrong component installed.... I know, I know, I had some words....

When I finally got the board back, it didn't survive, and is completely DOA.

So.....
I finally got some new boards in as my originals went belly up.

The first 2 boards I tested (Vsys = 8V) gave me LDO5, LDO3v3, Buck1, 2, and 5, but Buck 6 was at @ 5+V. The chip was in a reset cycle as well. Note that only CTL4 was active, the others were low.

I removed my test board which has the feedbacks on it. On ONE board, I then jumpered Feedbacks 2,3, and 6 on the power board directly (tied each to their respective o/p's)
I ended up with the same result.

Looking at Avnet's Ultra96 board, I notice they used 2.37k for ILIM6, and thought... what the heck...
However, after replacing the 1.18k, I lost the entire chip! no outputs at all except LDO5 = 0V, LDO3v3 =~1.5V, even with CTL4 low.

I haven't done anything with the other board yet as I don't understand what is happening with these things. I have followed proper anti static procedures, but the  IC's seem VERY fragile!

I am not sure if it's an assembly issue or what.

I have one semi-working pcb, and one more untested board which I would prefer not to kill! Do you have any ideas where to look now to get these working?

Craig

Hi Craig,

Unfortunately, when it comes to IC damage / fragility, there's not much I can say besides a few considerations. Especially considering that we have very few reports of IC instability that don't end up coming from some soldering issue or test board parasitics.

• ESD or EOS (Electrical Overstress) is certainly a possibility when trying to test the part but without a pattern to follow in the damaged ICs, we are left with guess-work on this front
• I believe there are issues with having the ILIM resistor value too low but it sounds like you replaced ILIM6 with a larger value resistor which would move you farther from any issues, so I'm not sure why the entire chip would be damaged. Keep in mind that the RILIM value is calculated based on expected ripple conditions from the voltage and inductor choices.

For further analysis I would need to see some more scope captures of the power sequence. I looked at the schematic again and the passive components appear to be within our recommendations.

What voltage are you measuring at the FBVOUT6 pin of the IC (directly next to the PMIC) when BUCK6 is regulating at 5+V?

Regards,

James

Hi James

Thanks for the i/p.

The feedback pin is essentially reading the same as buck6...5+V. which, AFAIK, should be connected to buck6 out to generate 1.8V

FYI, my last board seems to exibiting the same behaviour... I get Buck 1,2,and 5

Hi Craig,

Try replacing the ILIM6 resistor with something above 4k Ohms. Use something like 9k on ILIM6, similar to BUCK1. That way we can make sure this isn't an issue with ILIM6 being too low.

Regards,

James

HI James. Will do.

I also had a thought and am wondering if my load board got damaged when the current short circuited a few weeks back. I went ahead and measured the INPUT to the LT2991 on the test board (the one connected to buck6) (with my power board removed) and was reading ~1.5V.... Obviously an input pin should not have voltage on it with nothing connected to it. Unfortunately, we had already powered up my new batch of boards. I am getting 2 repaired and should be back tomorrow. I went and removed ALL my measurement components from the test board. I am hoping that is my current issue. I will let you know

Craig