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TPS6521905: Variation in power sequencing between various pcb having TPS6521908

Premalatha Royappan
Intellectual 910 points
Part Number: TPS6521905
Other Parts Discussed in Thread: TPS65219

Hi

We are using PMIC TPS6521908 in our design. 

We are observing some differences in the Power down sequence of PMIC between various DC boards, while trying to capture waveforms as part of DVT.
The ramp down of the voltages w.r.t Reset happens simultaneously and not after 10ms(refer snapshot below from TPS6521908_TRM). We understand that discharge duraon depends on Vout, Cout and load. But we want to know why we are seeing this difference between boards. Also is the timing duration specified in trm, a maximum limit? Pls let us know.
I have pasted here below ,captures for a couple of voltage rails for your reference.
board 1: (10 ms delay is observed between reset and all power rails(except for 1.1V) during power down sequence as per TRM)
board2: (No delay is observed between reset and all power rails during power down sequence) - not as per TRM
 
Additionally, we want to know how to measure this power down sequence of GPO2 w.r.t VSYS.  Is this VSYS at pmic input or the output of power switch?
(Please note :- To measure power down sequence we have connected a tactile switch at the PMIC enable pin and pressing it to disable the pmic. )
Kindly provide your inputs on the above two queries
  • 0
    TI__Genius 10772 points

    Hi Premalatha,

    The device expert is currently out of the office until tomorrow. They will look into this and provide a response when they return. Please expect a delay in response accordingly.

    Thanks,
    Field

  • 0
    TI__Mastermind 22521 points

    Hi,

    Thank You for using E2E! Based on the information provided in the previous message, the board #1 executes an orderly power-down sequence matching the TPS6521908 TRM and board #2 executes an immediate power-down with all rails turning OFF simultaneously. There are four key items that affect the power-down sequence: the voltage level on the pre-regulator that supplies VSYS, the external capacitance/load, the BYPASS_RAILS_DISCHARGED_CHECK register setting and any faults. Since the problem in your design seems to be more related to the sequencing order, then we could suspect the voltage on VSYS goes below the UVLO threshold before the PMIC completes the power-down sequence or the PMIC is detecting a fault during power-down. 

    Could you add the VSYS voltage to the scope captures in your previous message? Do you see any interrupt in the interrupt source register (INT_SOURCE, address 0x2B)?

    To read the interrupt register you would have to pull the Enable pin back to high so PMIC can transition to Active state. 

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    Intellectual 910 points

    Hi Brenda,

    Thanks for your response. We had further discussions on this issue internally and got to know such a power down use case is not applicable w.r.t our design. Hence we haven't continued our analysis on this further, at this point of time. 

  • 0 in reply to Premalatha Royappan
    TI__Mastermind 22521 points

    Hi,

    Thanks for sharing an update! If the information in my previous message answered your questions, feel free to click on the "resolved" option so we can close this ticket. You can always get back to the same ticket or submit a new one if additional support is needed. 

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    Intellectual 910 points
    Hi Brenda
    We are unable to reproduce the power down sequence issue which we observed previously,however we want to understand if it is of any concern.
     i,e if the rails which needs to be sequenced down after 10ms w.r.t nreset is not happening ,but goes down together along with nreset (as per the below snapshot)is it of any concern? Pls let us know.
  • 0 in reply to Brenda Diaz
    Intellectual 910 points
    Hi Brenda
    We are unable to reproduce the power down sequence issue which we observed previously,however we want to understand if it is of any concern.
     i,e if the rails which needs to be sequenced down after 10ms w.r.t nreset is not happening ,but goes down together along with nreset (as per the below snapshot)is it of any concern? Pls let us know.
  • 0 in reply to Premalatha Royappan
    TI__Genius 10772 points

    Hi Premalatha,

    The device expert is currently out of the office until next week. They will look into this and get you a response when they return. Please expect a delay in their response accordingly.

    Thanks,
    Field

  • 0 in reply to Field Tolson
    TI__Mastermind 22521 points

    Hi,

    Thanks for your patience! An immediate or orderly power-down does not affect the PMIC but might have consequences on the reliability of the processor. PMIC executes a sequenced power-down as long as the voltage on VSYS is present until the power-down sequence is complete. I would recommend checking with the processor team about the consequences (if any) of not following the expected power-down sequence from the AM62. Here is the link to the processor forum:

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum

    Thanks,

    Brenda