Impossible to erase the flag HSC or HOCD of bq78pl116

Hi Julien,

Please please looke at section on HOCD in the PL116 Technical Reference Manual to ensure you are following the recommended usage methodoogy.

The HOCD will persist indefinitely if the Over Current Condition exist.

Note the PL114 uses a 5milli-Ohm sense resistor whilst in the PL116, this sense resistor value is assignable in the .tmap file.

Hi Benjamin,

It has been almost two years I work on bq78pl114, I know how the chip works!
I'm not on my first try !
Especially on this function hardware.
Its operation is not correct on the bq78pl114.

The formulas are not correct !!! 

Me, I made the tests, like the technician :

View : http://e2e.ti.com/support/power_management/battery_management/f/180/p/99597/348826.aspx#348826

And view video of my test with EVM (1mOhm)

http://www.youtube.com/watch?v=1XiQqfW-Jtk

The phenomenon does not always occur in the first short-circuit.

I have not received a satisfactory answer.

Provide me a serious help, please.

Hi Julien,

Just realized I had not responded. My apologies.

I do agree that the equation is not accurate. However, the table is correct and the step size and tolerance should be accurate.

I can speculate the following from the symptoms you have described:

Depending on the setting of your Hardware Short Circuit Threshold, you should yield a current threshold of  (4.96 + (your seeting-37)*0.992) (Note there is a tolerance of ~+/-2A)

So you have to ensure that the current at which the fault is induces is "far" away from the current at whic it is removed. The hysterisi should be much greater than the tolerance.  

Also, the  Hardware Short Circuit Time  translates to a timing of (H/W Short Time * 104uS). If this timing is too short it might cause the the HSC to  trigger just from “inrush” currents as the FETS close.

I will propose you  increase this timing to the max to see if the issue goes away. You can then decrease the value to an optimal value for their pack.

Hope this helps.

Regards,

Ben

Hi Benjamin,

Thank you for your answer.

1) Impossible erase HSC or HOCD

We ordered a second evalboard to repeat the test, which was already the same board, and the first evalboard.

The setting of  Hardware Short Circuit Time is 31. The maximum value.

2) Inrush current

To date, I good know the chip, but maybe, I do not understand some parameters.

Although it seems that the values ​​speaks for itself.

The bq78pl114 (in production), we can not exceed the 23A. Whateverthe settings. 

Thank you for looking at the attached documents. We do not understand the results.

4251.PV515.xlsx

Hi Julien,

I came across this post that might be helpful.

http://e2e.ti.com/support/power_management/battery_management/f/180/p/110123/489189.aspx#489189

Regards,

Ben

Hi Julien,

Maybe I'm late on this here, but I have had the same problems during the last month. Even the support from TI was not able to help me but I just figured out that the HSC is working under the following conditions:

1. If the short circuit occurs then the HSC will let the FETs to be open

2. The BQ78PL116 is probing the packs terminals for the recent status after "hardware short circuit recovery" elapses (the fets are closing during a very short time-frame)

3. Normally I'd expect the 116 to close the FETs after removing the short - but it isn't. Instead the probing continues infinite

4. To solve this the short must remain beyond the first probing  of the terminals (in my case/example: >3sec)

DUT-setup: BQ78PL116EVB + BQ24610EVM + 12V/60A PSU + 30W load

working example:

Have a nice day,

Ole