Full Bridge Phase Shift ZVS Converter

KK,

Your statement

From my understanding, The initial current is the same for both secondary windings because the initial condition is that the primary winding voltage is zero due to the secondary current.

This is  incorrect. Just because the voltage is zero does not mean that the current is zero and in fact the voltage is not zero.

At the point in time when Qa turns off there has been a circulating current in the primary driven by the leakage inductance in the primary Lr and a reflected secondary current in the D1 diode driven by the reflection of the primary current and by the secondary inductance of that winding (not shown) and being pulled from the secondary by Lo.

The currents in the secondary outputs wiil not be the same as the secondary leakage inductances will not have had teh same current through them at teh start of the transition and will require some outside influence to change them. The impedances on the primary side will have done something to create a transition as will the forward volt drop of the diodes themselves but this will not be a great deal.

For the transition from Qa on to Qb on consider Lr and the primary winding of T1 as separate devices.

When Qa turns off Lr is still pulling current.  Consider that the voltage across the primary of T1 is still zero so you are driving the whole of the primary winding from the upper rail to the lower rail by the effect of Lr and the current primary current. This requires energy to transition Ca and CB so the current will start through Lr will start to decrease.

As long as energy in Lr is greater than the energy needed to transition the voltage of the effective capacitors Ca and Cb from one rail to the other you will get a resonant transition. Once that is established the voltage across the primary will re-establish itself.

Hi John,

Thanks for your explanation.

It is stated in the attached pdf as well that "Current in the conducting output rectifier D1 stays constant until t1. Since the voltage across the secondary winding collapses to zero, both output rectifiers will now share the full load output current Iout equally. Current in the rectifier that was previously off will quickly rise to Iout/2, while current in the previously conducting rectifier decays by a similar rate to Iout/2."

From the above statement, we know that during the duration t1 to t2, currents flow through D1 and D2 is the same which is Iout/2. This is because during this duration, voltage across the secondary winding is zero.

But, in the pdf file, it is stated that "initially, at t2, full load current is forced by primary resonant inductor Lr to flow in one of the secondary windings and in the other secondary."

My question is that at t2, the current flows in D1 is Iout or Iout/2?

Thank you.

Regards,

KK

KK,

Let me revise the previous statement and give a more detailed explanation.

I've modified a figure from the UCC28950 documentation (Fig. 2 of  SLUA560C) . The design is similar to the one you are discussing except that it uses synchronous rectifiers instead of didoes. I  took the diagram and modified the waveforms with RED lines.

The current through the secondary will depend on the di/dt of the primary current and the di/dt of the output inductor current reflected to the primary.

If you look at the initial picture showing the currents in the synchronous rectifiers you can see that if one output rectifier is carrying the current to the output when the power pulse stops (Both sync rectifiers get turned on) the current out of the rectifier that was conducting continues to conduct but the one that was not conducting is now conducting in the reverse direction. This is because(1)  there is near zero volts across both the primary and secondary. and (2) the primary has a larger leakage current than the secondaries and (3) the di/dt of the secondary, when the tuns ratio is taken into account, is greater than the di/dt on the primary. The difference becomes a circulating current coming out one winding on the secondary side and going back into the other.

Now if we change the synchronous rectifiers with diodes that reverse path is not available..and we get the same waveforms for the time during the "ON" time (QA and QD are both on) but when they turn off the output inductor forces current out of the secondary and since the di/dt of this current when reflected to the primary is greater than the primary current di/dt it creates a voltage on across the primary to decrease the current in the primary. This voltage is reflected to the primary driving the voltage on the anode of teh diode what was conducting even high and the voltage on the othere winding low.

This results in only one of the diodes conducting, therefore at T2 it is Iout.

The only time that both didoes would conduct would be if the di/dt of the output inductor when reflected to the primary was lower than the di/dt caused by the impedance of the primary side interaction with the leakage inductance.

Regards,

Hi John,

Thanks for your explanation. I am clear that during T1 to T2 duration, current flow into D1 is Iout while into D2 is zero.

I capture one of your paragraph above as below.

If you look at the initial picture showing the currents in the synchronous rectifiers you can see that if one output rectifier is carrying the current to the output when the power pulse stops (Both sync rectifiers get turned on) the current out of the rectifier that was conducting continues to conduct but the one that was not conducting is now conducting in the reverse direction. This is because(1)  there is near zero volts across both the primary and secondary. and (2) the primary has a larger leakage current than the secondaries and (3) the di/dt of the secondary, when the tuns ratio is taken into account, is greater than the di/dt on the primary. The difference becomes a circulating current coming out one winding on the secondary side and going back into the other.

How does the larger primary leakage current becomes the factor for reverse direction? How does point 3 becomes the factor for the reverse direction as well?

Can you explain in detail?

Thank you.

Regards,

KK

KK,

See attached file.

Regards.

Hi John,

Thanks for your detailed explanation. I am clearer now.

Just would like to confirm with you for below captured sentence.

This is not true for the secondary current. But with an ideal transformer the primary and secondary currents have to maintain the same ratio.

Because of the voltage on the output the voltage through Lo will start to decrease.

Should the bold letter of ' voltage' in the above sentence be 'current'?

Below is another question regarding 'Designing a Phase Shifted ZVT Power Converter' page3-6'.

"As soon as the left leg transition begins to take place the output inductor disappears from the circuit, removed by a basically short circuited transformer secondary"

How does the output inductor disappear by a short circuited transformer secondary?

If the output inductor can disappear by a short circuited transformer secondary, the output inductor can disappear during T1 to T2 as well. This is because we can see from Fig. 12 that during T1 to T2, Vpri is 0V and then transformer secondary should be 0V as well.

Thank you.

Regards,

KK

Hi John,

From Fig.12 in the pdf I attached earlier, it is shown that from T2 to T3, the Vpri is negative. This mean that Secondary winding voltage is reversed in negative voltage as well.

But in your statement, it is mentioned that "When this happens,  the voltage across the secondary stays at zero and current is drawn from both diodes in such a manner as to keep the primary and total secondary currents balanced."

Does you mean that from T2 to T3, the voltage across secondary is zero? Which one is correct?

Thank you.

Regards,

KK

Hi John,

Thanks for your explanation. I am clear now.

Below is another question regarding the demagnetizing path of the main transformer primary.

For example, as per my understanding, in a simple flyback converter, the primary demagnetizing path when the power switch is off, is flowing through the primary winding and back to the other end of the magnetizing inductance.

The demanetizing path is in blue colour as shown in the attached word file.

7331.Demagnetizing path of the Main Transformer of the Flyback Converter.docx

Please correct me if It is incorrect.

For the full bridge or phase shift full bridge, is the demagnetizing current flowing through the primary winding of main transformer and back to the other end of the magnetizing inductance without going through the parasitic diode of Qc?

Can you show the demagnetizing current path of this phase shift full bridge converter in a diagram and picture in different power switches off periods?

Thank you.

Regards,

KK

KK,

In the diagram the magnetizing inductance is not shown. This inductance is significantly larger than the other inductances in the transformer   which have been discussed. I have added it to the schematic (attached) and enclosed the transformer within a box. 

Since it has negligible impact on operation and is not a major contributor to the operation I have no intention of spending a significant amount of time producing the associated waveforms.

Regards,

Hi John,

Thanks for the schematic attached.

Can you help on my previous posted question as below without associated waveform?

For the full bridge or phase shift full bridge, is the demagnetizing current flowing through the primary winding of main transformer and back to the other end of the magnetizing inductance without going through the parasitic diodes of power switches?

Below is another question regarding the UC3879.

From the application note - 'U-154', the Tdelay = 249.6x10^-12/Idelay (sec). It is mentioned there the Vdelayset typically is 2.4V. Then, Tdelay = 1.04x10^-10xRdelay (sec).

But from SLUS230B, Delay time = 0.89x10^-10xRdelay (sec). Which formulae should I follow?

Thank you.

Regards,

KK

Hi John,

Thanks for the clarification on the delay time.

I understand the magnetizing current and the parallel magnetizing inductance but I am a bit confused about the demagnetizing current path. This is why I posted my previous question as below.

For the full bridge or phase shift full bridge, is the demagnetizing current flowing through the primary winding of main transformer and back to the other end of the magnetizing inductance without going through the parasitic diodes of power switches?

The Demagnetizing current flows in Path 1 or Path 2 (Please refer to the 'Demagtizing Current.bmp' file)?

Thank you.

Regards,

KK

Hi John,

Thanks for your explanation.

From my understanding, the current through Lmag in blue only happens when the voltage across the primary of the ideal transformer is zero. Is this correct?

As you said, 'it always has the option of going through the primary of the ideal transformer and appearing on the secondary.' Then, does this mean that during the voltage across primary of the ideal transformer is zero (from T2 to T3), current flowing through D2 will be a bit more than current through D1?

Thank you.

Regards,

KK

Hi John,

What does 'linear duty cycle range' mean in the UC2879 datasheet - SLUS230B? And what does 'upper end' of linear duty cycle range mean?

We are trying to choose the RT value for UC2879.

For the capacitor value of SS, can we just choose 220nF? We saw in TI Design Review, it is 1uF.

Thank you.

Regards,

KK

Hi John,

As you said, Dlin is the maximum duty cycle. If I would like to set the maximum duty cycle at 80%, then the Rt value is 1.25KOhm which is lower than the minimum recommended pulse width. Is it that we should not design the transformer duty cycle lower than 90%? The reason that I keep some margin on the duty cycle is to avoid overlapping of gate pulses which would lead to the damage of the Mosfets.

Thank you.

Regards,

KK

KK,

That Rt value sets an absolute maximum duty cycle and the width of the sync pulse. Your control loop will set the duty cycle but if you have a transient that maximum duty cycle will not be exceeded.Your delay circuit should prevent any overlap on each side.

Regards

Hi John,

Thanks for the clarification.

Here I have another question.

In the Deisgn Review of 500W Phase Shifted ZVT Converter, it is stated that 'With 1.1A ripple current at 200KHz, the acceptable ripple voltage component will be 25mV.'

Why the ripple component can be 25mV since it is stated that maximum output ripple is 100mVpp?

It is stated there that 'Cout(min) = I(p-p) / (8 x fconv x dVout)'

Why dVout = 25mV? Where does this formulae from? Why need to devide by '8' as shown in the formulae?

Thank you.

Regards,

KK

Hi John,

Kindly refer to the attached 500W EVM from TI.

Thank you.

Regards,

KK4555.Design Review - 500W 40WperIn3 Phase Shifted ZVT Power Converter (TI).pdf

KK,

The formula is derived from the change in voltage on a capacitor through the charge and discharge of a capacitor.

Assume that you have 50% duty cycle and that the peak to peak current is Ipp

Using the formula to identify the area under a triange to get the charge Q=.(5*Ipp/2)*t where t is half the 1/Fo you get

dV=(1/2)*(ipp/2)*(1/2)*1/fo*(1/Cout)  switching Cout and dV you get Cout= Ipp/(8*Fo*dVout)

This is the ripple from the charge and discharge of the capacitor.

The remaining ripple voltage is from the ESR of the capacitor.

Regards,

Hi John,

Let's take this attached current waveform of a output choke of a full bridge converter as example.

The switching frequency, Fo = 200KHz. To = 5us. Assume Duty cycle is 50%, then Ton = 2.5us. During Ton = 2.5us, dI = Ipp. By taking the slope-rising triangle into calculation, then Q = 0.5 x dI x 0.5/Fo = 0.5 x Ipp x 0.5/Fo.

But your formula is Q = 0.5 x (Ipp/2) x 0.5/Fo. Why there is (Ipp/2) in your formula while mine is only Ipp?

Another question is why the dVout = 25mV while maximum spec for peak to peak ripple voltage is 100mVpp? Do you mean that 25mV ripple voltage is due to the charge and discharge of output capacitor while the 75mV is due to the ESR of the output capacitor? What is the selection criteria for this 25mV and 75mV?

Thank you.

Regards,

KK

Hi John,

The Vcap = 25mV is due to the dI = Ipp/2, then Vcap peak to peak is 50mVpp. But we assume Vesr = 75mVpp. The total peak to peak ripple voltage = 50mVpp + 75mVpp = 125mVpp which is > 100mVpp, the maximum specification.

If the Vcap is 25mV, then Vesr assumed should be 50mVpp. The % selection for Vcap peak to peak and for Vesr from the maximum specification of peak to peak ripple voltage is 50%.

Thank you.

Regards,

KK

Hi John Botrill,

For CCM (Continuous Current Mode), we need to allocate a fixed resistor at the output and this resistor value is mainly determined by the output inductance. And this resistor value is affected by the output capacitance as well.

Is there any formula related between the output capacitance value and the output resistor value once the output inductance value is fixed?

Thank you.

Regards,

KK

Hi John,

Is it possible to reduce the min load needed for CCM by increasing output capacitance?

Thank you.

Regards,

KK

Hi John Bottrill,

Based on the 'Discontinuous Conduction Brings Issues to Current-mode Converters' paper in EDN, it is stated that

'First, establish the feedback components from the control IC’s COMP pin back to the sensor/amplifier. You must take into account the range of voltage that the COMP pin requires. This portion requires a constant gain of four. The error-amplifier sensor circuit must have a gain of 0.5 at 5kHz, and the gain should be nearly flat at 1 and 25 kHz. You tailor the gain shape around the error amplifier.'

1) What does this sensor/amplifier refer to?

2) How does the required range of the COMP pin voltage affect the selection of feedback components?

3) What does This portion refer to?

4) Why the error-amplifier sensor circuit must have a gain of 0.5 at 5kHz, and the gain should be nearly flat at 1 and 25 kHz. You tailor the gain shape around the error amplifier?

Can you include circuitries for the answers above?

By the way, is there any guide for the components selection on COMP pin and EA- pin of the UC2879?

Thank you.

Regards,

Kok Khuan

Hi John Bottrill,

For the answer of no.2, "You can't arrange for the comp to swing 5 volts if the total range where it will impact the current sensor is much less. Given the numbers in the daa sheet below you should be able to determine teh voltage limits where the COMP voltage will have an impact."

Does it mean that COMP voltage will have impact on the CS pin? Why & How it can impact CS? Then why do we need to have the impact of COMP voltage to CS?

Frankly, for http://www.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=slua122&fileType=pdf, it does not guide me to select the components on COMP and EA- pins. Is it possible that you can point out any part inside this document that can help me on this?

Thank you.

Regards,

KK 

KK,

The "magnetizing current"  is not a real current in any particular winding. It is the FLUX within the core and manifests itsself as a current in what ever winding is the most convenient. For instance if both output diodes were to be conducting then it would "push" one to conduct a little more than the other.

If the "B" and "C" switches are bothon and there is a not exact turns ratio difference between the primary and secondary currents the difference is the result of the magnetizing current.

If you look at the primary and assign the magnetizing current to that then the mag current would increase in one direction when "A" and "D" are on and decrease When "B" and "C" are on. In a perfect system it would not change during the freewheeling time.

Regards,

John

Hi John,

I measured the phase/gain on my phase-shift full bridge board and found out that the phase margin could be reduced by increasing the value of snubber capacitors at the 2ndary-side rectifier diode.

Why is this so?

Regards,

KK