TPS546D24A: Layout Review

Shifali N 

Joseph asked me to help him out with this layout review.  I'm going over the details, and I'm concerned about the lack of separate grounds between the PGND and AGND creating some bypassing issues.

U6 has the VSHARE bypass capacitor connected to the ground plane rather than back to Pin 37 (AGND).  It would be much better if this was routed back to Pin 37 on the top layer rather than to the GND plane and up to AGND through the thermal pad as was done in U7 and U8.

The layout of the VSHARE bypass capacitor is slightly different for each device, but the best layout would be U8, with the capacitor direcly between the pins, though the added via above C43 should be removed.

U8 and U7 are using via in pad for their Vshare capacitors to route VSHARE while U6 has a trace to the via.  While either is fine, the via in pad configuration makes for a tighter layout.  If the via in pad is adding cost, the U8 layout would make a small trace to the via fairly simple

The Pin programming resistors for MSEL1, MSEL2, VSEL, and ADRSEL should be connected to the AGND pin not through the ground plane.  Noise in the ground plane from other converters and devices could affect the accuracy of the pin detection and create start-up issues.

There appear to be 5 0402 capacitors from VCC_5V to GND near the PVIN of each of the converters, but all of them are routed away from the part.  I would recommend moving 2 of them  between the VCC_5V vias and the GND vias of the power pad directly under the PVIN pins.  These capacitors should be between 2.2nF and 10nF.  These capacitors have self-resonnace near the self-resonance frequency of the switching node, and enough ESR to be self-damping.  (Example from under U6 shown, but should be repeated on all 3 devices)

It also looks like AVIN is bypassed to GND.  AVIN should be bypassed to AGND.  Routing the AVIN to AGND connection through the thermal pad can introduce some operational issues, especially for VIN = 5V.

Via locations relative to the output capacitors appears to be different for the different phases, with U6 and U7 having via in pad for the ground side output capacitors and U8 via in pad for the VOUT side.  U8 also has additional VOUT vias near the capacitors.  I would recommend making these all the same.  The more vias that can be placed close to the capacitors, the better the performance wil generally be, however I would caution against placing groups of vias so close that internal ground layers can not fill in between the vias, as the "slots"  in the ground will significantly increase the ground impedance.  

U6 and U8 have the input ground and output ground connected at the IC pin, but this appears to be missing from U7, I would recommend including it for U7

I would recommend extending the ground on top and bottom as close to VOUT as design rules allow to expand the ground area for thermal dissipation.  If design rules allow for vias under the package body and between the package terminals, this can significantly reduce parasitic inductance and improve transient performance and stability.

U7 and U8 both have 2 vias for PB1V5.  This does not need 2 vias and can really be 1. Additionally, U7 could have it's rounded on the top layer like U6 is, so that VSHARE can be routed from U7 to U6 on the same layer it was routed from U8 to U7.

It looks like BCX_CLK is shorted to a ground via by VSHARE of U6, unless this is a blind via.

The far right side of the output pour, furthest away from the load is likely not the best place for the remote sense source point, nor is routing the return path under the switching node side of the TPS546D24A.  I would recommend a remote sense point closer to the loading processor for better load regulation (output voltage drop as loading current increases) and keeping the routing away from the switching node to avoid noise coupling.

Peter James Miller said:

The far right side of the output pour, furthest away from the load is likely not the best place for the remote sense source point, nor is routing the return path under the switching node side of the TPS546D24A.  I would recommend a remote sense point closer to the loading processor for better load regulation (output voltage drop as loading current increases) and keeping the routing away from the switching node to avoid noise coupling.

The layout has the connection point from VOUT to VOSNS on the lower right corner of the VOUT pour while the load is left will result in an output voltage load-line equal to the resistance in the traces between the sense point and the load due to the I×R drop between the sense point and the load.

Moving the output voltage sense point to the left, or even to the FPGA itself, would help improve regulation over load.  If needed, the VOSNS point can be connected to several spots around the FPGA with the same resistance to average the voltage across the entire FPGA area.  Each point to be averaged should be connected to a common feedback line to VOSNS with the same resistance, such as 50 or 10 ohms.  The TPS546D24A will then regulate the average across those several points.

Shifali N said:

2. Also, whether C44, R98, R96, R97 and R95 should be placed near FPGa or regulator. Please confimr.

For the best performance, keep C44, R96, and R98 close to the IC, this will maximize the effectiveness of their filter on noise into the feedback loop.

R97 and R95 should be placed close to the FPGA to provide differential sensing.

If you want to add averaging across several points, increase R97 and R95 to 10Ω and add additional 10-Ω resistors in parallel with R95 and R97 to collect to the other sense points.

It may also be useful to add a capacitor from FPGA_CORE_0V85 at the current location of R97 to the common net between R97 and R98 to allow for the phase-lag due to inductance in the power-path of FPGA_CORE_0V85 to the sense points by the FPGA.