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LM5155: SEPIC Layout Tips/Guide for 4 layer PCB design

Deniel Go
Intellectual 340 points
Part Number: LM5155

Hello TI Engineers,

I would like to know if you have any guide documents on the layout of the LM5155 SEPIC design. Do we just based it on the LM5155 SEPIC EVM? Do you have the Gerber files for that board?

The EVM is only a 2 layer board design but we are planning to add it in our main 4 layer PCB design (that has other analog, power and digital circuits). Currently in our existing PCB design, the 2 inner layers are full ground planes.

How should we go about integrating the LM5155 SEPIC layout design? Do we make sure that the analog ground plane section of the LM5155 circuit is not connected to our main ground planes in the inner layers?

The reason why we have a full inner layer ground planes is that most of the current circuits we have did not require a separate ground planes.

Thanks,

Deniel

  • 0
    TI__Guru 59415 points

    Hello Deniel,

    We do not have specific layout documentation for a SEPIC converter, but if you go to our website and search for PCB layout guidelines, you will find several documents. Generic rules apply to the SEPIC, e.g. start with the high current loops and the high voltage nodes.

    There is no requirement for separate ground planes, it just makes it a lot easier to make sure that the high current areas are separated from the low current/high precision areas. If just one GND is used, it is very difficult to make sure that the power stage noise is not coupling into the feedback and compensation for example.

    We can share the Alium files as well as the gerbers, but this will take until at least end of the week.

    Best regards,
    Brigitte

  • 0 in reply to Brigitte
    Intellectual 340 points

    Hello Brigitte,

    Thanks for the response and clarification. I look forward to the Altium and Gerber files at the end of the week. 

    Regarding LM5155 EVM, the Exposed Pad eventually connects to the PGND plane on the top layer and the AGND has its own copper pour plane and is not connected to the main PGND plane. Can place Vias in the expose pad area and that connects to the Ground planes in the inner layers? And not connect the AGND copper plane to the inner layer ground planes?

    Can you explain further the this statement in the LM5155 datasheet layout example 1: "Do not connect input and output capacitor grounds underneath the device"

    Thanks,

    Deniel

  • 0 in reply to Deniel Go
    TI__Guru 59415 points

    Hello Deniel,

    High AC current flows from the input to the output capacitors, so make sure that the connection does not pass the IC.

    Nevertheless, the IC has to be connected to PGND and AGND.

    Best regards,
    Brigitte

  • 0 in reply to Brigitte
    TI__Expert 5035 points

    Hi Deniel, 

    Please give us some more time for the altium files.

    I will come backt to you until mid of next week.

    Thanks for you patience.

    Best regards,

    Moritz

  • +1 in reply to Moritz
    TI__Expert 5035 points

    Hi Deniel,

    please find the Altium and Gerber files attached:

    BMC030A-LM5155EVM-SEPIC.zip

    Best regards,

    Moritz