TPSF12C3QEVM: Choosing the correct chip component values (UPS)

Hi, I am an engineering student and I am currently doing an internship in a company that produces, among other products, UPS.

I have been provided with the TPSF12C3QEVM chip and a 20 KVA UPS. Despite having read all the documentation available on the official product page, used the calculations in the TPSF12C3-Q1 standalone document, and conducted various tests, I continue to get unsatisfactory results in EMC tests.

For the tests we chose not to use the bypass and batteries. The UPS can support a load of 20 KVA and during the tests I kept the UPS load at 75%. Based on the tool, I have a network capacity of 220 pF and a regulator capacity of 10 nF. The company’s engineers suggested keeping the ESR at 0.5. I use a LISN with an inductance of 50 µH and both at the input and output we use common mode inductors: at the input a ferrite (0.03 mH) and at the output nanocrystals (0.72 mH).

I conducted various tests, listed below:

1. Scan 6 - Initial situation without TPSF12C3 EVM chip
2. Scan 12 - Insertion of the chip without modifications - Csens = 560 pF and Cinj = 20nF - Addition of a capacitor between the GND and VCC power lines
3. Scan 17 - Csens 560 pF and Cinj = 20 nF - Chip modification with CD3=22 nF and CD1=3.7 nF
4. Scan 18 - Csens = 560 pF and Cinj = 15 nF - Chip with the same configuration as scan 17.
5. Scan 19 - Csens = 560 pF and Cinj = 4.7 nF - Chip with the same configuration as scan 17.
6. Scan 20 - Csens = 560 pF and Cinj = 4.7 nF - Chip modification with CD2 = 10 nF , CD1 = 1.5 nF and CD3 = 4.7 nF

(All tests were performed on the first phase).

As can be seen from the test results, these are very unsatisfactory. I wonder what can be done to improve or at least achieve the same results as scan 6. Could I have made mistakes in calculations? Could I have forgotten something?

I apologize if my question seems ignorant. If there is any further explanation beyond what I have already read, it would be very helpful for me.

In the original UPS board, there were Cys between the input and output CM inductors. To make the test reliable, we decided to remove them, in order to fully follow your instructions

I attach the link to access all the scans performed with also the comparisons.

https://drive.google.com/drive/folders/1T-ojFRtu7ZZZwrc_stXKObuetNeFScGW?usp=drive_link

Thank you in advance for your response.