[FAQ] TPSF12C1 and TPSF12C3 power-supply filter IC FAQs

Part Numbers: TPSF12C1/3/-Q1

TPSF12C1/-Q1 and TPSF12C3/-Q1 FAQ home page

This is the home page for common questions and collateral resources related to the TI's new family of power-supply filter ICs.

How do I get started with TI's power-supply filter ICs?

We provide a range of design resources, from starting-level content to help you get familiar with active EMI filter ICs, to more advanced collateral and tools to assist you through the design and evaluation process as you design your system with active EMI filtering. Here, we have a resource hub of available technical collateral:

Active EMI filter landing page:  Power-supply filter ICs

Technical whitepaper:  How active EMI filter ICs mitigate common-mode emissions and increase power density in single- and three-phase power systems

Technical article:  How a standalone active EMI filter IC shrinks common-mode filter size

Press release:  TI pioneers the industry's first stand-alone active EMI filter ICs, supporting high-density power supply designs

Video:  Single- and three-phase active EMI filter ICs mitigate common-mode EMI, save space and reduce cost

PCIM 2023 technical paper:  An active EMI filter for common-mode EMI mitigation in high-power AC systems

APEC 2023 technical paper:  An active EMI filter for high-power off-line applications

How2power.com article series:  How active EMI filters reduce common-mode emissions in single- and three-phase applications – Part 1: An overview;  Part 2: Modeling ferrite chokes;  Part 3: Modeling nanocrystalline chokes. Parts 4 and 5 (on loop stability analysis and filter design examples, respectively) are pending publication.

PCIM 2024 technical paper:  Analytical modeling and stability characterization of a damped active EMI filter for single- and three-phase AC-DC applications [pending release, June 2024].

What are the available tools and EVMs to assist with my design?

TI offers several EVMs, an Excel-based quickstart design calculator, a Mathcad design tool, as well as PSPICE, SIMPLIS and PSIM simulation models to assist with active EMI filter design.

Single-phase EVMs: TPSF12C1QEVM, TPSF12C1EVM-FILTER

Three-phase EVM:  TPSF12C3QEVM

Quickstart calculator:  TPSF12C1/-Q1 and TPSF12C3/-Q1 common-mode AEF quickstart calculator tool

Mathcad design tool:  TPSF12C1/-Q1 and TPSF12C3/-Q1 common-mode AEF mathcad design file

SIMPLIS simulation models:  Single phase and three phase

PSPICE simulation models:  Single phase and three phase

Noteworthy E2E threads:  Single-phase SIMPLIS simulation with 50µH LISN

What is the design flow for AEF?

Refer to the EVM user's guides for substantial detail on the AEF design flow. Here are the steps:

1. Use the TPSF12C1/3 quickstart calculator as a convenient starting point for circuit design. Model the CM choke impedance using measured impedance (magnitude and phase) data or equivalent circuit model parameters. Ensure that the loop gain with the selected damping network components is stable by checking that the phase does not reach or go below –180°.
2. Avail of the provided PSPICE or SIMPLIS simulation models for the TPSF12C1 and TPSF12C3 devices. Use such models along with prepared test benches to investigate the operation of the complete active filter circuit.
3. Validate the filter design at low voltage prior to connecting to the switching regulator. This is a relatively easy step to confirm various aspect of the design, including filter stability, insertion loss (or filter attenuation), voltage swing on the IC's INJ pin, and EMI performance with CM signal excitation.
4. Validate the filter design while connected to the high-voltage switching regulator. Separate the DM and CM noise such that the benefit of CM noise reduction can be clearly seen. Measure the INJ pin voltage and verify it does not saturate, especially near the AC line current zero-crossings where low-frequency disturbances can occur in totem-pole PFC designs (when the MOSFETs in the line-frequency leg change state) or in three-phase designs when switching stops (creating high-impedance nodes subject to CM resonant perturbations).
   

Any tips for circuit optimization and debug?

Here are some considerations and best practices to optimize AEF circuit operation:

1. It is important to understand and quantify the relative contributions of modal noise components, DM and CM, in the total noise signature of the system, particularly in the 100 kHz to 3 MHz range where AEF mainly operates.
   • In an existing passive filter design where retrofit of AEF is being considered, check whether DM or CM noise is applicable on a quantitative basis, as the TPSF12C1/3 is only useful for CM noise mitigation. Use a DM/CM separator of the total noise measurement for this purpose. See the recommended circuit of Fig. 5 in Part 2 here if a noise separator is not available.
     
   • As a simple alternative test for a qualitative check, increase the X-capacitance and Y-capacitance independently to reduce DM and CM noise, respectively, and review the effect on the total noise measurement from the LISN. For example, if higher X-capacitance makes no substantial difference to the total noise, then it can be inferred that DM noise presents a lower relative contribution and does not dominate the total noise signature. In this case, higher Y-capacitance (that mimics the addition of a CM AEF circuit) should also reduce the total noise if CM noise is applicable to the overall EMI signature.
     
2. If the EMI measurement with AEF enabled is not performing as expected, probe the INJ pin voltage (pin 13 of the IC) while the regulator is switching. Verify that the voltage at the INJ pin (the output of the AEF power amplifier) is not saturating near the positive or negative supply rails.
   • If saturation of the INJ pin voltage is observed, increase the VDD supply voltage, the regulator-side CM choke and/or Y-capacitance, and/or the inject capacitance. Then recheck the loop stability using the quickstart calculator or by simulation. Step 7 of the quickstart calculator predicts the INJ voltage swing amplitude based on inputs such as the switch-node voltage, CM noise source capacitance and switching frequency.
3. The metallic chassis structure is an absolutely critical part of the overall filter structure and implementation. The filter PCB typically mounts to the chassis structure using several screw attachments, and the chassis serves to connect the various GND nodes on the filter PCB. Often, these nodes are not explicitly connected with copper on the PCB and instead rely on the chassis to complete the electrical connection. As such, the chassis becomes the lowest impedance return path for CM noise current.
   • When testing a power stage that includes a chassis, CM noise can capacitively couple to the reference ground plane of the EMI measurement setup and thus bypass a filter circuit that is not closely referenced to this ground plane. In this case, TI recommends bonding the GND plane copper of the filter EVM directly to the reference ground plane. This also serves to minimize parasitic inductance in the GND connection to the AEF circuit. CM current emanating from the power stage then gets recirculated by the low shunt impedance of the filter Y-capacitors (both active and passive), thus preventing CM noise from reaching the LISN.
4. Based on the amplification of the effective Y-capacitance, AEF allows reduction of the CM choke inductance while maintaining the same LC corner frequency and CM attenuation characteristic. However, a choke with reduced CM inductance and smaller size normally has a lower leakage inductance, which is responsible for DM attenuation along with the X-capacitors.
   • If the DM inductance is significantly reduced with the smaller CM chokes, then increase the X capacitance or add a small discrete inductor to obtain sufficient DM attenuation. Otherwise, a high DM noise component (relative to the CM component) can dominate the total noise measurement, therefore concealing the impact of AEF on CM noise mitigation.
5. Typical values for the sense and inject capacitances are 680pF and 4.7nF (single phase) / 22nF (three phase), respectively. Depending on the final implementation in the target application, the default damping and compensation component values installed on the EVM can require modification by the user to achieve acceptable loop stability. Note that nanocrystalline chokes with their softer impedance phase characteristic and stable properties over temperature are preferable and inherently easier to stabilize than their ferrite-cored equivalents.