TPS6521905: Power down sequence depending on load current

Hi Nishie,

Thank You for using our E2E forum. The load and output capacitance are key external factors that affect the power-down sequence because they also define how fast (or slow) the rail discharges and goes below the SCG threshold. 

The higher the load, the faster the rail discharges below the SCG threshold. If the output voltage goes below the SCG threshold before the slot duration expires, the PMIC will still wait until the slot duration finishes.  

If register setting "BYPASS_RAILS_DISCHARGED_CHECK" is changed before the the power-down sequence is executed, the timing measurements between slots will be the same with load or no load. Let us know if you have any questions or need additional information.      

Thanks,

Brenda

Hi Nishie-san,

The next output voltage (Vout_n+1) starts to power down after both conditions are met (previous rails are below SCG threshold and previous slot duration is complete). If "BYPASS_RAILS_DISCHARGED_CHECK" is changed, then PMIC ignores the SCG threshold during power-down. In this scenario, the slot duration would be the only condition to power-down the next rail in sequence.    

Please note the power-down slot duration is measured from the time Vout_n starts to power down until Vout_n+1 starts to power-down. 

Thanks,

Brenda