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Layout has a lot to do with the ability to pass electrical surge testing. Is the transformer shielded? Does the application have a film capacitor from the bulk voltage to the primary ground? All bypass capacitors must be as close to the IC pins as possible with very short traces in order to be effective. Keep the controller as close to the FET as possible and minimize the power loops.
It is very important that all input traces are kept as far away from the FB,CS, VS and DRV pins. I suspect that transient energy is coupled into one of these pins in the customer's design.
I would also check to see which pins are damaged during this testing as it can give an idea where the surge energy is getting trapped.
Generally, the surge signal has three possible paths: through the Y1 EMI capacitor between primary and secondary grounds, through the transformer from secondary ground to primary ground, or through the transformer from secondary ground to the primary bulk positive rail. The pcb design must divert the surge signal on the primary ground (which is the combination of the first two paths mentioned above) away from the UCC28742. The best way to do this would be to use a "star" ground connection for the various ground paths: the small signal IC ground, the high-current current sense ground, the input bridge rectifier ground, the MOSFET heatsink, transformer AUX winding ground, and the input bulk capacitor. Each of these ground traces should be separate and connect only at the bulk input capacitor to form the star connection. Also, to improve immunity to the surge, make the ground traces as thick as possible because the fault signal amplitude is directly related to the impedance of the PCB traces.
