Other Parts Discussed in Thread: TPS51200
Dears,
I’m a HW guy from Syntronic. My colleague Zeya Guo has contacted you before. We are using TPS51200QDRCRQ1 ( TPS51200-Q1) and have a confusion need your confirmation. The schematic is as below.
In this case we don’t use VTT_0P6V_EN ( controlled by other chip ) to enable the chip, DC_3V3 and V_1P2V rails are ramped up at the same time. In other words, in our design, DC_3V3 ,V_1P2V, VTT_0P6V_EN are ramped up at the same time. In TPS51200 datasheet the tracking sequence is as below. VLDOIN ( V_1P2V ) should followed by EN (VTT_0P6V_EN) and 3.3VIN (DC_3V3).
If this can’t be met the datasheet descripted VLDOIN can ramp up earlier than VIN, so it means there is no sequence requirements on 3.3VIN and VLDOVIN. So our design is this scenario and can meet the datasheet description.
But I don’t find this description in datasheet of TPS51200-Q1, only descripted sequence should follow figure 20 . So there is a difference on power supply sequence description. Fron my understanding only difference between TPS51200 and TPS51200-Q1 is temperature range.
Pls help us to confirm that whether our power up sequence can be used in TPS51200-Q1 ? BTW there is no problem found in our current design, but DDR stress test has not been done yet.
Can this paragraph in the description of TPS51200 datasheet be applied to my design (I use TPS51200-Q1) (my timing is VLDOIN>VIN3.3/EN, EN is pull-up to VIN3.3, So the timing between VIN3.3 and EN is synchronized tracking).
