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Original question:

BQ25792: Schematic check request

BQ25792: Schematic and Layout Review

Filip Lupas
Prodigy 20 points
Part Number: BQ25792

Hello to the TI support community!
The following is a kind request for a quick review of the schematic and layout and a sanity check of the design decisions. 

The charger can be configured for 1S/2S/3S operation with 9V to 15V input voltages and a maximum of 3A input current (USB-C PD input negotiated upstream). 
The battery pack is connected with around 5cm of cabling to the board connector which is near the charging circuitry connected with a wide plane. A fuel gauge measures the battery temperature and current. 

1. Was there at any point a benefit in adding a small series resistance to the bootstrap capacitors for EMI considerations (any testing done on previous EVMs)? And if so, is there a recommended value?
2. Given the short battery wiring and the added 47nF capacitor on BATP, should there be any issues with hotplugs? I understand that the 5usec time constant (with 100R series) is there to delay the startup of the SHIP FET such that any other capacitances can be charged, is this faulty reasoning? 
3. The JEITA charging profile will be implemented in software by adjusting the fast charge current register (as the fuel gauge reads the temperature). Is it sufficient if TS pin is tied low to stop charging until any software takes control and sets TS_IGNORE? Also, during production, before software is loaded, are there any caveats in injecting a voltage into TS to trick the charger into thinking a thermistor is attached and test the functionality (gated by REGN perhaps)?

Layout: 

The bootstrap capacitors are placed on the bottom layer of the board. The 2nd layer is solid GND and the distance between layer 1 and 2 is 0.14mm with a Dk of 4.2. Total board has 4 layers with 1.55mm thickness. 
4. On this particular board, there are some other sensitive components on it and there was a concern in dropping the switching node through the entire board two times (as in EVM). The high dv/dt of the switching node was considered to be more easily managed and that is why only the bootstrap capacitors are on the bottom side (so the high di/dt of the switch node is maintained on the top layer). Is this a decent compromise or are my assumptions incorrect? 
5. There were references to a previous EVM that had issues due to vias in the loop of the HF capacitors (on SYS/PMID). Given the above implementation, the stackup and the design constraints, would this layout, at least by comparison with the old EVM, potentially perform better? Note that the main return pin of the charger for the power stage is tied with multiple vias spread on both sides to minimize at least half of the loop inductance associated with the HF loops.
6. If there are any other notes about the layout that I did not ask about, but consider are important, please mention them.

Thank you and Best Regards,
Filip.  

  • 0
    TI__Guru**** 155056 points

    Hi Filip,

    Schematic looks good.  

    Regarding 1, bootstrap resistor should be no larger than 10 ohms or there will be a large efficiency decrease. I have had little success using series bootstrap resistors to lower EMI.  RC snubbers from SWx to ground can almost always be tuned to eliminate any EMI.

    Regarding 2, the 47nF on BATP is likely not needed since you only have 3S battery. 

    Regarding 3, you can hardware disable TS using matching resistor for the resistor divider from REGN to ground.

    Regarding 4 and 5, the previous EVM had a similar layout with the 0.1uF PMID and SYS caps being via'd on one side.  This resulted in the charge current sensing amp reading too high and charge current not reaching max.  If your charge current is low (<2.5A) your layout might be okay but the charge current accuracy may be out of spec.

    Regarding 6, unfortunately, the only layout I can recommend is the one in the datasheet and EVM with SW nodes via'ing down and back up.  The 0.1uF SYS and PMID caps to GND without vias also help reduce EMI.

    Regards,

    Jeff

  • 0 in reply to Jeff F
    Prodigy 20 points

    Hi Jeff,
    Thank you for the extensive review, really appreciate it. 

    This is more out of curiosity but would really appreciate hearing your thoughts on it. 
    In the datasheet block diagram, ICHG is taped from the top of BATFET, between SYS and BAT nodes. I would then assume that voltage noise due to the high current loop through the 0.1uF cap on SYS and ground is the one influencing the ICHG reading, right? And in an symmetrical way, Iin would be influenced on the PMID 0.1uF cap (or maybe not?). 

    IF we use this charger as a buck converter only (in which my assumption is that SW2 is not switching) and NEVER in boost mode, could we connect the SYS 0.1uF as in the EVM with a direct connection to ground, and have only PMID 0.1uF connected through a via with SW2 also going through a via since it is never switching? That would neatly solve all issues for this very particular configuration.

    Best Regards,
    FIlip. 

  • 0 in reply to Filip Lupas
    TI__Guru**** 155056 points

    Hi Filip,

    Your assumption is correct. The current sense amp for the BATFET was the main issue.  On the input side, the FET between VBUS and PMID uses the same type of current sense amplifier as the BATFET.  During testing, we saw that the input current limit was slightly out of spec on the few units tested.  There may be other units where the input current measurement is too high and therefore also limits output power.

    Regards,

    Jeff 

  • 0 in reply to Jeff F
    Prodigy 20 points

    Hi Jeff, thank you for the response. And is this out of spec limit on top of the IINDPM accuracy numbers? Is there some causality here where some proclivity of the IIN current reading to be high results in the input current regulation to not hit its spec across the entire current range (Figure 8-17 from DS)?
     
    Regards,
    Filip. 

  • 0 in reply to Filip Lupas
    TI__Guru**** 155056 points

    Hi Filip,

    Out of spec means not meeting the accuracy range per the elec spec table and the figure above.  On the BATFET side, the current sense amp fed back a higher current value than was actually flowing due to the switching noise not being filtered by the 0.1uF capacitor. I would expect the same behavior on the input side so the charger could report IINDPM and enter supplement mode even though the actual input current is below IINDPM setting.  The opposite could also occur, but less likely, where the charger's input current is higher than the IINDPM setting but the input current sense amp measured incorrectly.  Luckily on the input side, the VINDPM loop would activate and prevent input source collapse.

    Regards,

    Jeff