• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 2 answers
  • Subscribers 63 subscribers
  • Views 192 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TPS3820: Operation when /RESET=Low

TPS3820: /RESET is released by turning off the power

Yuta Nishie
Genius 3410 points
Part Number: TPS3820
Other Parts Discussed in Thread: TPS3823, TPS3828, , TPS3824

Hi,

In the same state as the question in the following thread, is it correct to recognize that after /RESET=Low is fixed (Latch), /RESET is released by turning off the power?

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1305196/tps3820-operation-when-reset-low/4962662?tisearch=e2e-sitesearch&keymatch=%25252520user%2525253A460063#4962662

Best Regards,

Nishie

  • 0
    TI__Genius 11301 points

    Hi Nishie -san 

    There are 3 situlations where /RESET can go low - 

    • VDD < VIT- 
      • RESET will go high after TD time once VDD is >= VIT
    • MR is pulled low 
      • RESET will go high after TPHL once MR is pulled high 
    • WDI time out event 
      • If there is no pulse on WDI pind in the time out duration, RESET will hgo low for TD time and will come up. WD timer will restart and WDI pin will again look for WDI pulse. 

    Regards 

    Trailokya 

  • 0 in reply to Trailokya Rai
    Genius 3410 points

    Hi Trailokya-san,

    Thank you for your support.

    Does your answer apply even after/RESET is stuck as below?

    ・Datasheet P15, 8.3.4 Watchdog Timer (WDI)

    "In applications where the input to the WDI pin is active (transitioning high and low) and the TPS3820, TPS3823, TPS3824, or TPS3828 is asserting RESET, RESET is stuck at a logic low after the input voltage returns above VIT–. "

    Best Regards,

  • 0 in reply to Yuta Nishie
    TI__Genius 11301 points

    Nishi-san , 

    My previous reply was for the case where WDI is not monitored when RESET is asserted. And systems gets rebooted in td time. 

    I you want to monitor WDI pulse when RESET is asserted, the you need external FET as shown in figure 9-3 or use A version as mentioned in the data sheet 

    Regards

    Trailokya 

  • 0 in reply to Trailokya Rai
    Genius 3410 points

    Hi Trailokya-san,

    Thank you for your quick answer.

    I understand that you need to use an external FET or A version.

    My question was assuming that/RESET gets stuck with logic Low when you are not using an external FET or A version. In this case, is/RESET unstuck by restarting the IC?

    Best Regards,

    Nishie

  • +1 in reply to Yuta Nishie
    TI__Genius 11301 points

    Yuta San 

    That is correct asumption. 

    Regards

    Trailokya